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1. 发明授权

US08749293B2 Stackable programmable passive device and a testing method 失效
标题翻译：可堆叠可编程无源器件和测试方法
公开(公告)号：US08749293B2
公开(公告)日：2014-06-10
申请号：US13529557
申请日：2012-06-21
申请人： Fen Chen , Douglas D. Coolbaugh , Baozhen Li
发明人： Fen Chen , Douglas D. Coolbaugh , Baozhen Li
IPC分类号： G06G7/19 , H01L29/00
CPC分类号： H01L27/101 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.
摘要翻译：一种包括第一节点和第二节点的可编程无源设备。电耦合到第一节点的多个无源器件元件。多个开关电耦合到至少第二节点并且选择性地耦合到多个无源器件元件，以向可编程无源器件提供预定值。

2. 发明授权

US08642460B2 Semiconductor switching device and method of making the same 失效
标题翻译：半导体开关器件及其制造方法
公开(公告)号：US08642460B2
公开(公告)日：2014-02-04
申请号：US13155757
申请日：2011-06-08
申请人： Chih-Chao Yang , Stephen A Cohen , Baozhen Li
发明人： Chih-Chao Yang , Stephen A Cohen , Baozhen Li
IPC分类号： H01L21/44
CPC分类号： B82Y10/00 , H01L23/5252 , H01L29/413 , H01L2924/0002 , H01L2924/00
摘要： A switching device including a first dielectric layer having a first top surface, two conductive features embedded in the first dielectric layer, each conductive feature having a second top surface that is substantially coplanar with the first top surface of the first dielectric layer, and a set of discrete islands of a low diffusion mobility metal between the two conductive features. The discrete islands of the low diffusion mobility metal may be either on the first top surface or embedded in the first dielectric layer. The electric conductivity across the two conductive features of the switching device increases when a prescribed voltage is applied to the two conductive features. A method of forming such a switching device is also provided.
摘要翻译：一种开关装置，包括具有第一顶表面的第一介电层，嵌入在第一介电层中的两个导电特征，每个导电特征具有与第一介电层的第一顶表面基本上共面的第二顶表面，以及一组在两个导电特征之间的低扩散迁移率金属的离散岛。低扩散迁移率金属的离散岛可以在第一顶表面上或嵌入在第一介电层中。当规定的电压施加到两个导电特征时，开关装置的两个导电特征的电导率增加。还提供了一种形成这种开关装置的方法。

3. 发明授权

US08421186B2 Electrically programmable metal fuse 有权
标题翻译：电子可编程金属保险丝
公开(公告)号：US08421186B2
公开(公告)日：2013-04-16
申请号：US13149108
申请日：2011-05-31
申请人： Baozhen Li , Chunyan E. Tian , Chih-Chao Yang
发明人： Baozhen Li , Chunyan E. Tian , Chih-Chao Yang
IPC分类号： H01L29/00 , H01L23/525 , H01H37/76
CPC分类号： H01L23/5256 , G11C17/16 , G11C29/785 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.
摘要翻译：金属电可编程保险丝（eFuse）包括在金属条的两端处具有与宽金属线部分相邻的金属线的具有宽度大于金属带宽度的宽度的金属带。条带宽度可以是光刻最小尺寸，并且金属条带的长度与条带宽度的比率大于5以在编程期间定位围绕金属条的中心的加热。加热的本地化减少了用于编程金属eFuse所需的电力。此外，在金属带的长于Blech长度的部分内的编程期间形成逐渐的温度梯度，使得金属的电迁移在金属带的中心部分逐渐发生。金属线部分提供与金属eFuse相同的水平，以物理阻挡编程期间产生的碎屑。

4. 发明申请

US20120261724A1 STACKABLE PROGRAMMABLE PASSIVE DEVICE AND A TESTING METHOD 失效
标题翻译：可堆叠可编程被动设备和测试方法
公开(公告)号：US20120261724A1
公开(公告)日：2012-10-18
申请号：US13529557
申请日：2012-06-21
申请人： Fen Chen , Douglas D. Coolbaugh , Baozhen Li
发明人： Fen Chen , Douglas D. Coolbaugh , Baozhen Li
IPC分类号： H01L23/52 , H01L21/326
CPC分类号： H01L27/101 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.
摘要翻译：一种包括第一节点和第二节点的可编程无源设备。电耦合到第一节点的多个无源器件元件。多个开关电耦合到至少第二节点并且选择性地耦合到多个无源器件元件，以向可编程无源器件提供预定值。

5. 发明申请

US20120119366A1 ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT 有权
标题翻译：通过电路互连连接
公开(公告)号：US20120119366A1
公开(公告)日：2012-05-17
申请号：US13356013
申请日：2012-01-23
申请人： Baozhen Li , Paul S. McLaughlin , Timothy D. Sullivan
发明人： Baozhen Li , Paul S. McLaughlin , Timothy D. Sullivan
IPC分类号： H01L23/532
CPC分类号： H01L21/76816 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.
摘要翻译：在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触重叠变化。

6. 发明授权

US08114768B2 Electromigration resistant via-to-line interconnect 有权
标题翻译：防电互连线路互连
公开(公告)号：US08114768B2
公开(公告)日：2012-02-14
申请号：US12344838
申请日：2008-12-29
申请人： Baozhen Li , Paul S. McLaughlin , Timothy D. Sullivan
发明人： Baozhen Li , Paul S. McLaughlin , Timothy D. Sullivan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.
摘要翻译：在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触重叠变化。

7. 发明申请

US20110115508A1 DETERMINING CRITICAL CURRENT DENSITY FOR INTERCONNECT 失效
标题翻译：确定互连的关键电流密度
公开(公告)号：US20110115508A1
公开(公告)日：2011-05-19
申请号：US12620955
申请日：2009-11-18
申请人： Chad M. Burke , Cathryn J. Christiansen , Baozhen Li
发明人： Chad M. Burke , Cathryn J. Christiansen , Baozhen Li
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： Solutions for determining a critical current density of a line are disclosed. In one embodiment a method of determining a critical current density in a line includes: applying a temperature condition to each of a plurality of samples including the line; calculating a cross-sectional area of the line for each of the plurality samples using data about an electrical resistance of the line over each of the temperature conditions; measuring an electrical current reading through the line for each of the plurality of samples; determining a current density through the line for each of the plurality of samples by dividing each electrical current reading by each corresponding cross-sectional area; determining an electromigration (EM) failure time for each of the plurality of samples; and determining the critical current density of the line using the current density and the plurality of EM failure times.
摘要翻译：公开了用于确定线的临界电流密度的解决方案。在一个实施例中，确定线中的临界电流密度的方法包括：对包括线的多个样本中的每一个施加温度条件; 使用关于在每个温度条件下的线的电阻的数据来计算多个样本中的每个样本的线的横截面面积; 测量所述多个样本中的每一个的所述线的电流读数; 通过将每个电流读数除以每个对应的横截面积来确定通过所述多个样品中的每一个的所述线的电流密度; 确定所述多个样本中的每一个的电迁移（EM）故障时间; 以及使用电流密度和多个EM故障时间确定线路的临界电流密度。

8. 发明授权

US07500208B2 Non-destructive evaluation of microstructure and interface roughness of electrically conducting lines in semiconductor integrated circuits in deep sub-micron regime 有权
标题翻译：在深亚微米体系的半导体集成电路中的导电线的微结构和界面粗糙度的非破坏性评估
公开(公告)号：US07500208B2
公开(公告)日：2009-03-03
申请号：US11673369
申请日：2007-02-09
申请人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
IPC分类号： G06F17/50 , G01R31/26
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.
摘要翻译：用于评估半导体集成电路中的线路的新型结构和方法。在每个包括多个线段的晶片上形成第一组多条线。所有线段长度相同。测量线路段的电阻。然后，基于所有部分的电阻来确定第一行几何调整。第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。相同长度和厚度的第二组多条线可以形成在同一晶片上。然后，基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

9. 发明授权

US08726201B2 Method and system to predict a number of electromigration critical elements 失效
标题翻译：预测一些电迁移关键要素的方法和系统
公开(公告)号：US08726201B2
公开(公告)日：2014-05-13
申请号：US12780138
申请日：2010-05-14
申请人： Jeanne P. Bickford , Peter A. Habitz , Baozhen Li , Paul S. McLaughlin , Dileep N. Netrabile
发明人： Jeanne P. Bickford , Peter A. Habitz , Baozhen Li , Paul S. McLaughlin , Dileep N. Netrabile
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/10
摘要： A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors.
摘要翻译：一种用于预测半导体产品中多个电迁移关键元件的方法和系统。该方法包括使用运行在计算机设备上的设计工具并且基于增加的可靠性温度和增加的预期电流中的至少一个来确定电路设计库中的多个库元件的关键要素因子。该方法还包括：（i）产品中包含的多个库元素中的相应数量的数量，以及（ii）关键要素因素来确定产品中的关键元素的数量。

10. 发明申请

US20140048927A1 METHOD TO IMPROVE FINE CU LINE RELIABILITY IN AN INTEGRATED CIRCUIT DEVICE 有权
标题翻译：在集成电路设备中提高精细线路可靠性的方法
公开(公告)号：US20140048927A1
公开(公告)日：2014-02-20
申请号：US13587998
申请日：2012-08-17
申请人： Chad M. Burke , Baozhen Li , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Chad M. Burke , Baozhen Li , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76847 , H01L21/76838 , H01L21/76843 , H01L21/76844 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Structure and methods for forming a semiconductor structure. The semiconductor structure includes a plurality of layers comprising at least one copper interconnect layer. The copper interconnect layer provides an electrical conduit between one of physically adjacent layers in the semiconductor structure and an integrated circuit in the semiconductor structure and an electronic device. A plurality of studs is positioned within the at least one copper interconnect layer. The studs are spaced apart by a distance less than or equal to a Blech length of the at least one copper interconnect layer. The Blech length is a length below which damage due to electromigration of metal atoms within the at least one copper interconnect layer does not occur. The plurality of studs comprises copper atom diffusion barriers.
摘要翻译：用于形成半导体结构的结构和方法。半导体结构包括包括至少一个铜互连层的多个层。铜互连层在半导体结构中的物理相邻层之一和半导体结构中的集成电路和电子器件之间提供电导体。多个螺柱被定位在所述至少一个铜互连层内。螺栓间隔开小于或等于至少一个铜互连层的Blech长度的距离。漂浮长度是低于该值的长度，在该长度之下不会发生由于至少一个铜互连层内的金属原子的电迁移而导致的损伤。多个螺柱包括铜原子扩散阻挡层。

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