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41. 发明授权

US06406956B1 Poly resistor structure for damascene metal gate 有权
标题翻译：镶嵌金属门的聚电阻结构
公开(公告)号：US06406956B1
公开(公告)日：2002-06-18
申请号：US09845483
申请日：2001-04-30
申请人： Ming-Hsing Tsai , Chii-Ming Wu
发明人： Ming-Hsing Tsai , Chii-Ming Wu
IPC分类号： H01L218238
CPC分类号： H01L27/0629 , H01L28/20 , H01L29/66545
摘要： A layer of gate oxide and polysilicon are deposited over the surface of a substrate, these layers are etched to create a dummy gate and a resistor. Spacers are formed on the dummy gate and the resistor, suitable impurities are implanted self-aligned with the dummy gate. A layer of dielectric is deposited and polished down to the surface of the dummy gate and the polysilicon resistor, the dummy gate is removed creating an opening in the layer of dielectric. A high-k dielectric is deposited over which a layer of metal is deposited, the surface of the layer of metal and high-k dielectric are polished down to the surface of the layer of dielectric leaving in place a metal gate electrode and a polysilicon resistor.
摘要翻译：在衬底的表面上沉积一层栅极氧化物和多晶硅，蚀刻这些层以产生伪栅极和电阻器。间隔物形成在虚拟栅极和电阻器上，合适的杂质被注入与伪栅极自对准。电介质层沉积并抛光到虚拟栅极和多晶硅电阻器的表面，去除伪栅极，在电介质层中形成开口。沉积高k电介质，在其上沉积金属层，金属层和高k电介质的表面被抛光到介电层的表面，留下原位金属栅电极和多晶硅电阻。

42. 发明授权

US06399486B1 Method of improved copper gap fill 有权
标题翻译：铜间隙填充方法
公开(公告)号：US06399486B1
公开(公告)日：2002-06-04
申请号：US09442313
申请日：1999-11-22
申请人： Sheng-Hsiung Chen , Ming-Hsing Tsai
发明人： Sheng-Hsiung Chen , Ming-Hsing Tsai
IPC分类号： H01L2144
CPC分类号： H01L21/2885 , H01L21/76882
摘要： The present invention teaches a special annealing process to “heal” electrochemical copper deposited (ECD) defects in a dual damascene via and trench structure. The annealing step is processed after the electrochemical deposition (ECD) of the top excess copper and before the chemical mechanical polishing (CMP) of the copper. The key processing steps of this invention are the special annealing steps at key temperatures, ambient, pressures and times to anneal out the defective copper voids in the dual damascene structure. These annealing conditions are special annealing steps to promote low temperature copper surface diffusion to “heal” the voids and other defectives within the copper trench and via structure. The special annealing conditions of: temperature, ambient, pressure and time are the following: temperature in a range of about 300 to 500° C., ambient of nitrogen N2, hydrogen H2 gases (reducing atmosphere to remove copper oxide, N2/H2 plasma preferred), pressure in a range of about 100 MPa to 600 MPa, time in a range of about 0.5 to 10 minutes. These conditions are designed to take advantage of low temperature surface diffusion mechanisms.
摘要翻译：本发明教导了一种特殊的退火方法，以在“双镶嵌”通孔和沟槽结构中“治愈”电化学铜沉积（ECD）缺陷。退火步骤在顶部多余铜的电化学沉积（ECD）和铜的化学机械抛光（CMP）之前进行。本发明的关键处理步骤是关键温度，环境温度，压力和退出双镶嵌结构中缺陷铜空隙的时间的特殊退火步骤。这些退火条件是促进低温铜表面扩散以“愈合”铜沟槽和通孔结构内的空隙和其它缺陷的特殊退火步骤。温度，环境温度，压力和时间的特殊退火条件如下：温度在约300至500℃的范围内，氮气环境N2，氢气H 2气体（还原气氛以除去氧化铜，N 2 / H 2等离子体优选），压力在约100MPa至600MPa的范围内，时间在约0.5至10分钟的范围内。这些条件被设计为利用低温表面扩散机制。

43. 发明授权

US06319831B1 Gap filling by two-step plating 有权
标题翻译：间隙填充通过两步电镀
公开(公告)号：US06319831B1
公开(公告)日：2001-11-20
申请号：US09507904
申请日：2000-02-22
申请人： Wen-Jye Tsai , Ming-Hsing Tsai
发明人： Wen-Jye Tsai , Ming-Hsing Tsai
IPC分类号： H01L2144
CPC分类号： H01L21/2885 , H01L21/76877
摘要： A multi-step electrochemical method for forming a copper metallurgy on an integrated circuit which has high aspect ratio contact/via openings is described. The method is designed to give good coverage and gap filling capability as well as high production throughput by depositing the copper in two stages with an optional dwell period between the stages. The process utilizes a copper plating electrolyte which contains an added brighteners and levelers. A first copper layer is plated at a low current density which provides good coverage resulting from a high throwing power. The high aspect ratio openings are covered with a substantial thickness of a uniform, high quality copper coating. During plating, the concentration of brightener becomes depleted in the base region of high aspect ratio contacts or vias. Optionally, the brightener is replenished in these regions during a brief dwell period wherein the plating current is stopped. Next, a high current density is applied whereby the openings are filled and additional copper is deposited over them at a high deposition rate. A benefit of the high current density deposition is that depletion of leveler chemical in the openings enhances the growth rate of copper at the base of the openings thereby favoring growth from bottom up. This avoids the formation of voids in the openings. The greatest throughput benefits are realized, by way of the high current density step, when the process is applied to the formation of a dual damascene metallurgy.
摘要翻译：描述了在具有高纵横比接触/通孔开口的集成电路上形成铜冶金的多步电化学方法。该方法设计为通过在两个阶段之间以可选的停留时间两段沉积铜来提供良好的覆盖和间隙填充能力以及高的生产量。该方法使用含有添加的增白剂和矫光剂的镀铜电解质。第一铜层以低电流密度电镀，由高投掷功率提供良好的覆盖。高长宽比的开口用相当厚度的均匀的高质量铜涂层覆盖。在电镀期间，增亮剂的浓度在高纵横比触点或通孔的基极区域中耗尽。任选地，在电镀电流停止的短暂停留期间，增白剂在这些区域中补充。接下来，施加高电流密度，由此填充开口并且以高沉积速率在其上沉积附加的铜。高电流密度沉积的益处在于开口中矫正剂化学品的消耗增加了开口底部的铜的生长速率，从而有利于从下到上生长。这避免了在开口中形成空隙。通过高电流密度步骤，当该方法应用于双镶嵌冶金的形成时，实现了最大的生产效率。

44. 发明授权

US06274484B1 Fabrication process for low resistivity tungsten layer with good adhesion to insulator layers 有权
标题翻译：低电阻率钨层的制造工艺，对绝缘体层具有良好的附着力
公开(公告)号：US06274484B1
公开(公告)日：2001-08-14
申请号：US09527184
申请日：2000-03-17
申请人： Ming-Hsing Tsai , Sheng-Hsiung Cheu
发明人： Ming-Hsing Tsai , Sheng-Hsiung Cheu
IPC分类号： H01L214763
CPC分类号： H01L21/76886 , H01L21/28079 , H01L29/66545
摘要： A process for forming a low resistivity tungsten layer, for use as a metal gate structure, or a metal damascene structure, has been developed. The process features initial deposition of a metastable tungsten nitride layer, via a plasma enhanced, or metal organic chemical vapor deposition procedures, resulting in good adhesion, in addition to good step coverage, of the tungsten nitride layer, to underlying or adjacent insulator layers. The high resistivity, tungsten nitride layer is then converted to a lower resistivity tungsten layer, via a rapid thermal anneal procedure, performed in an argon ambient, or in vacuum.
摘要翻译：已经开发了用于形成用作金属栅极结构的低电阻率钨层或金属镶嵌结构的工艺。该方法特征在于通过等离子体增强或金属有机化学气相沉积方法初始沉积亚稳态氮化钨层，除了氮化钨层的良好的步骤覆盖之外，还可以向下面或相邻的绝缘体层提供良好的附着力。然后通过快速热退火工艺将高电阻率的氮化钨层转化为较低电阻率的钨层，在氩气环境或真空中进行。

45. 发明授权

US08785321B2 Low resistance and reliable copper interconnects by variable doping 有权
标题翻译：低电阻和可靠的铜互连可变掺杂
公开(公告)号：US08785321B2
公开(公告)日：2014-07-22
申请号：US13249823
申请日：2011-09-30
申请人： Ting-Chu Ko , Ming-Hsing Tsai , Chien-Hsueh Shih
发明人： Ting-Chu Ko , Ming-Hsing Tsai , Chien-Hsueh Shih
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.
摘要翻译：提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层金属合金互连件均保持材料均匀性。

46. 发明授权

US07544281B2 Uniform current distribution for ECP loading of wafers 有权
标题翻译：晶圆的ECP负载均匀电流分布
公开(公告)号：US07544281B2
公开(公告)日：2009-06-09
申请号：US11119183
申请日：2005-04-28
申请人： Ming-Wei Lin , Ming-Hsing Tsai
发明人： Ming-Wei Lin , Ming-Hsing Tsai
IPC分类号： C25D5/02
CPC分类号： C25D17/06 , C25D5/18 , C25D7/123 , C25D17/001 , C25D17/005 , H01L21/2885
摘要： An electrochemical plating apparatus and method for facilitating uniform current distribution across a wafer during loading into an ECP (electrochemical plating) apparatus is disclosed. The apparatus includes a bath container for containing a bath solution, an anode provided in the bath container, a cathode ring for supporting a wafer in the bath container and a current source electrically connected to the anode and the cathode ring. According to the method, a voltage potential is applied to the cathode ring as it is immersed into the solution and prior to immersion of the wafer in the solution, thereby facilitating a substantially uniform plating current across the wafer upon immersion of the wafer.
摘要翻译：公开了一种用于在装载到ECP（电化学电镀）装置中时促进在晶片上均匀分布电流的电化学电镀装置和方法。该装置包括用于容纳浴溶液的浴容器，设置在浴容器中的阳极，用于在浴容器中支撑晶片的阴极环和与阳极和阴极环电连接的电流源。根据该方法，当阴极环浸入溶液中并且在将晶片浸入溶液之前，电压电势被施加到阴极环上，从而有助于在晶片浸入时跨晶片的基本均匀的电镀电流。

47. 发明授权

US07235482B2 Method of manufacturing a contact interconnection layer containing a metal and nitrogen by atomic layer deposition for deep sub-micron semiconductor technology 有权
标题翻译：通过用于深亚微米半导体技术的原子层沉积来制造包含金属和氮的接触互连层的方法
公开(公告)号：US07235482B2
公开(公告)日：2007-06-26
申请号：US10657505
申请日：2003-09-08
申请人： Chii-Ming Wu , Ming-Hsing Tsai , Ching-Hua Hsieh , Shau-Lin Shue
发明人： Chii-Ming Wu , Ming-Hsing Tsai , Ching-Hua Hsieh , Shau-Lin Shue
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L21/28562 , H01L23/53261 , H01L2924/0002 , H01L2924/00
摘要： An atomic layer deposition method is used to deposit a TiN or TiSiN film having a thickness of about 50 nm or less on a substrat. A titanium precursor which is tetrakis(dimethylamido)titanium (TDMAT), tetrakis(diethylamido)titanium (TDEAT), or Ti{OCH(CH3)2}4 avoids halide contamination from a titanium halide precursor and is safer to handle than a titanium nitrate. After a monolayer of the titanium precursor is deposited on a substrate, a nitrogen containing reactant is introduced to form a TiN monolayer which is followed by a second purge. For TiSiN, a silicon source gas is fed into the process chamber after the TiN monolayer formation. The process is repeated several times to produce a composite layer comprised of a plurality of monolayers that fills a contact hole. The ALD method is cost effective and affords an interconnect with lower impurity levels and better step coverage than conventional PECVD or CVD processes.
摘要翻译：使用原子层沉积方法在基底上沉积厚度约为50nm或更小的TiN或TiSiN膜。作为四（二甲基氨基）钛（TDMAT），四（二乙基氨基）钛（TDEAT）或Ti（OCH 2 CH 3）2） 4避免了来自卤化钛前体的卤化物污染，并且比硝酸钛更安全。将钛前体的单层沉积在基底上之后，引入含氮反应物以形成TiN单层，随后进行第二次吹扫。对于TiSiN，在TiN单层形成之后，将硅源气体进料到处理室中。该过程重复几次以产生由填充接触孔的多个单层组成的复合层。 ALD方法具有成本效益，并且提供了比常规PECVD或CVD工艺更低的杂质水平和更好的阶梯覆盖的互连。

48. 发明申请

US20070054488A1 Low resistance and reliable copper interconnects by variable doping 有权
标题翻译：低电阻和可靠的铜互连可变掺杂
公开(公告)号：US20070054488A1
公开(公告)日：2007-03-08
申请号：US11341827
申请日：2006-01-27
申请人： Ting-Chu Ko , Ming-Hsing Tsai , Chien-Hsueh Shih
发明人： Ting-Chu Ko , Ming-Hsing Tsai , Chien-Hsueh Shih
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.
摘要翻译：提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层金属合金互连件均保持材料均匀性。

49. 发明申请

US20060199379A1 Method for forming dual damascene structures with tapered via portions and improved performance 有权
标题翻译：用于形成具有锥形通孔部分的双镶嵌结构和改进的性能的方法
公开(公告)号：US20060199379A1
公开(公告)日：2006-09-07
申请号：US11071104
申请日：2005-03-04
申请人： Ming-Shih Yeh , Ming-Hsing Tsai , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Shih Yeh , Ming-Hsing Tsai , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/4763 , H01L21/31
CPC分类号： H01L21/76804 , H01L21/31144 , H01L21/314 , H01L21/76808 , Y10S438/978
摘要： The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer is formed above the conductive layer. An etching stop layer is formed above the protective layer and the first insulating layer. A second insulating layer is formed above the etching stop layer. A first patterned photoresist layer is formed above the second insulating layer, the first patterned photoresist layer having a first pattern. The first pattern is etched into the second insulating layer and the etching stop layer to form a first opening. A via plug is filled at least partially in the first opening. An anti-reflective coating (ARC) layer is formed above the second insulating layer. A second patterned photoresist layer is formed above the ARC layer, the second photoresist layer having a second pattern. The second pattern is etched into portions of the via plug, second insulation layer, and the ARC layer to form a second opening, wherein a substantially tapered sidewall portion is formed at the interface of the first and second openings.
摘要翻译：提供了具有改进的性能，特别但非限制性的双镶嵌结构的镶嵌结构的制造。在一个实施例中，具有导电层的衬底形成在第一绝缘层中。在导电层上形成保护层。在保护层和第一绝缘层上方形成蚀刻停止层。在蚀刻停止层上形成第二绝缘层。第一图案化光致抗蚀剂层形成在第二绝缘层之上，第一图案化光致抗蚀剂层具有第一图案。将第一图案蚀刻到第二绝缘层和蚀刻停止层中以形成第一开口。通孔插塞至少部分地填充在第一开口中。在第二绝缘层上方形成抗反射涂层（ARC）层。第二图案化光致抗蚀剂层形成在ARC层上方，第二光致抗蚀剂层具有第二图案。第二图案被蚀刻到通孔塞，第二绝缘层和ARC层的部分中以形成第二开口，其中在第一和第二开口的界面处形成大致锥形的侧壁部分。

50. 发明授权

US06878615B2 Method to solve via poisoning for porous low-k dielectric 失效
标题翻译：解决多孔低介电常数中毒的方法
公开(公告)号：US06878615B2
公开(公告)日：2005-04-12
申请号：US09863224
申请日：2001-05-24
申请人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L2221/1063
摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.
摘要翻译：公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

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