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    • 1. 发明申请
    • Method for forming dual damascene structures with tapered via portions and improved performance
    • 用于形成具有锥形通孔部分的双镶嵌结构和改进的性能的方法
    • US20060199379A1
    • 2006-09-07
    • US11071104
    • 2005-03-04
    • Ming-Shih YehMing-Hsing TsaiShau-Lin ShueChen-Hua Yu
    • Ming-Shih YehMing-Hsing TsaiShau-Lin ShueChen-Hua Yu
    • H01L21/4763H01L21/31
    • H01L21/76804H01L21/31144H01L21/314H01L21/76808Y10S438/978
    • The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer is formed above the conductive layer. An etching stop layer is formed above the protective layer and the first insulating layer. A second insulating layer is formed above the etching stop layer. A first patterned photoresist layer is formed above the second insulating layer, the first patterned photoresist layer having a first pattern. The first pattern is etched into the second insulating layer and the etching stop layer to form a first opening. A via plug is filled at least partially in the first opening. An anti-reflective coating (ARC) layer is formed above the second insulating layer. A second patterned photoresist layer is formed above the ARC layer, the second photoresist layer having a second pattern. The second pattern is etched into portions of the via plug, second insulation layer, and the ARC layer to form a second opening, wherein a substantially tapered sidewall portion is formed at the interface of the first and second openings.
    • 提供了具有改进的性能,特别但非限制性的双镶嵌结构的镶嵌结构的制造。 在一个实施例中,具有导电层的衬底形成在第一绝缘层中。 在导电层上形成保护层。 在保护层和第一绝缘层上方形成蚀刻停止层。 在蚀刻停止层上形成第二绝缘层。 第一图案化光致抗蚀剂层形成在第二绝缘层之上,第一图案化光致抗蚀剂层具有第一图案。 将第一图案蚀刻到第二绝缘层和蚀刻停止层中以形成第一开口。 通孔插塞至少部分地填充在第一开口中。 在第二绝缘层上方形成抗反射涂层(ARC)层。 第二图案化光致抗蚀剂层形成在ARC层上方,第二光致抗蚀剂层具有第二图案。 第二图案被蚀刻到通孔塞,第二绝缘层和ARC层的部分中以形成第二开口,其中在第一和第二开口的界面处形成大致锥形的侧壁部分。
    • 2. 发明授权
    • Method for forming dual damascene structures with tapered via portions and improved performance
    • 用于形成具有锥形通孔部分的双镶嵌结构和改进的性能的方法
    • US07354856B2
    • 2008-04-08
    • US11071104
    • 2005-03-04
    • Ming-Shih YehMing-Hsing TsaiShau-Lin ShueChen-Hua Yu
    • Ming-Shih YehMing-Hsing TsaiShau-Lin ShueChen-Hua Yu
    • H01L21/44
    • H01L21/76804H01L21/31144H01L21/314H01L21/76808Y10S438/978
    • The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer is formed above the conductive layer. An etching stop layer is formed above the protective layer and the first insulating layer. A second insulating layer is formed above the etching stop layer. A first patterned photoresist layer is formed above the second insulating layer, the first patterned photoresist layer having a first pattern. The first pattern is etched into the second insulating layer and the etching stop layer to form a first opening. A via plug is filled at least partially in the first opening. An anti-reflective coating (ARC) layer is formed above the second insulating layer. A second patterned photoresist layer is formed above the ARC layer, the second photoresist layer having a second pattern. The second pattern is etched into portions of the via plug, second insulation layer, and the ARC layer to form a second opening, wherein a substantially tapered sidewall portion is formed at the interface of the first and second openings.
    • 提供了具有改进的性能,特别但非限制性的双镶嵌结构的镶嵌结构的制造。 在一个实施例中,具有导电层的衬底形成在第一绝缘层中。 在导电层上形成保护层。 在保护层和第一绝缘层上方形成蚀刻停止层。 在蚀刻停止层上形成第二绝缘层。 第一图案化光致抗蚀剂层形成在第二绝缘层之上,第一图案化光致抗蚀剂层具有第一图案。 将第一图案蚀刻到第二绝缘层和蚀刻停止层中以形成第一开口。 通孔塞至少部分地填充在第一开口中。 在第二绝缘层上方形成抗反射涂层(ARC)层。 第二图案化光致抗蚀剂层形成在ARC层上方,第二光致抗蚀剂层具有第二图案。 第二图案被蚀刻到通孔塞,第二绝缘层和ARC层的部分中以形成第二开口,其中在第一和第二开口的界面处形成大致锥形的侧壁部分。
    • 4. 发明授权
    • Method for improvement of gap filling capability of electrochemical deposition of copper
    • 改进铜电化学沉积间隙填充能力的方法
    • US06224737B1
    • 2001-05-01
    • US09377540
    • 1999-08-19
    • Ming-Hsing TsaiWen-Jye TsaiShau-Lin ShueChen-Hua Yu
    • Ming-Hsing TsaiWen-Jye TsaiShau-Lin ShueChen-Hua Yu
    • C25D502
    • H01L21/76877C25D3/38C25D5/48C25D7/123H01L21/2885H01L23/53238H01L2924/0002H01L2924/00
    • A semiconductor structure having a trench formed therein is provided. The semiconductor structure may be a substrate with an overlying interlevel metal dielectric layer having the trench. A voltage is applied to the trenched semiconductor inducing a bias field where there is a first field proximate the trench bottom and a second field, greater than the first field, proximate the trench's upper side walls and the semiconductor upper surface proximate the trench. The semiconductor structure is placed into an electroplating solution containing a predetermined concentration of brighteners and levelers. Because of the induced bias field, the brightener concentration is greater proximate the trench bottom and the leveler concentration is greater the trench's upper side walls and the semiconductor upper surface proximate the trench. A copper layer having a predetermined thickness is then electrolytically deposited within the trench in a “bottom-up” fashion and blanket fills the upper surface of the semiconductor structure. The structure may then be planarized by CMP to create a planarized copper filled trench.
    • 提供具有形成在其中的沟槽的半导体结构。 半导体结构可以是具有具有沟槽的上覆层间金属介电层的衬底。 电压被施加到沟槽半导体,其诱导偏置场,其中存在靠近沟槽底部的第一场和大于第一场,接近沟槽的上侧壁和靠近沟槽的半导体上表面的第二场。 将半导体结构放入含有预定浓度的增白剂和矫直剂的电镀溶液中。 由于感应偏压场,光滑剂浓度在沟槽底部附近较大,并且矫直剂浓度大于沟槽的上侧壁和接近沟槽的半导体上表面。 然后将具有预定厚度的铜层以“自下而上”的方式电解沉积在沟槽内,并且覆盖填充半导体结构的上表面。 然后可以通过CMP平面化该结构以产生平坦化的铜填充沟槽。
    • 7. 发明授权
    • Multi-step electrochemical copper deposition process with improved
filling capability
    • 多步电化学铜沉积工艺具有改善的填充能力
    • US6140241A
    • 2000-10-31
    • US270591
    • 1999-03-18
    • Shau-Lin ShueMing-Hsing TsaiWen-Jye TsaiChen-Hua Yu
    • Shau-Lin ShueMing-Hsing TsaiWen-Jye TsaiChen-Hua Yu
    • H01L21/288H01L21/768H01L21/302H01L21/461
    • H01L21/76877H01L21/2885
    • A multi-step electrochemical method for forming a copper metallurgy on an integrated circuit which has high aspect ratio contact/via openings is described. The method is designed to give good coverage and gap filling capability as well as high production throughput by performing the electrochemical deposition of copper in two deposition stages with an dwell period between the stages. The process utilizes a copper plating electrolyte which contains an added brightener and leveler. The first deposition is done at a low current density which provides good coverage resulting from a high throwing power. The high aspect ratio contact/via openings are covered with a substantial thickness of a uniform, high quality copper coating. During the deposition, the concentration of brightener becomes depleted in the base region of high aspect ratio contacts or vias. The concentration of brighteners, is replenished in these regions by diffusion during a brief dwell period wherein the plating current is stopped. Next, a high current density is applied whereby the contact/vias are filled and additional copper is deposited over them at a high deposition rate. The greatest throughput benefits are realized, by way of the high current density step, when the process is applied to the formation of a dual damascene metallurgy.
    • 描述了在具有高纵横比接触/通孔开口的集成电路上形成铜冶金的多步电化学方法。 该方法设计为通过在两个沉积阶段之间执行铜的电化学沉积,具有阶段之间的停留时间,以提供良好的覆盖和间隙填充能力以及高的生产量。 该方法使用含有添加的增白剂和矫直机的镀铜电解质。 第一次沉积以低电流密度进行,这提供了由高投掷功率引起的良好覆盖。 高长宽比的接触/通孔开口用相当厚度的均匀的高质量铜涂层覆盖。 在沉积期间,增亮剂的浓度在高纵横比触点或通孔的基极区域中耗尽。 增亮剂的浓度,在电镀电流停止的短暂停留期间通过扩散在这些区域补充。 接下来,施加高电流密度,由此接触/通孔被填充,并且以高沉积速率在其上沉积额外的铜。 通过高电流密度步骤,当该方法应用于双镶嵌冶金的形成时,实现了最大的生产效率。