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41. 发明授权

US07294580B2 Method for plasma stripping using periodic modulation of gas chemistry and hydrocarbon addition 有权
标题翻译：使用气体化学和碳氢化合物加成的周期调制的等离子体剥离方法
公开(公告)号：US07294580B2
公开(公告)日：2007-11-13
申请号：US10860833
申请日：2004-06-03
申请人： Seokmin Yun , Ji Zhu , Peter Cirigliano , Sangheon Lee , Thomas S. Choi , Peter Loewenhardt , Mark H. Wilcoxson , Reza Sadjadi , Eric A. Hudson , James V. Tietz
发明人： Seokmin Yun , Ji Zhu , Peter Cirigliano , Sangheon Lee , Thomas S. Choi , Peter Loewenhardt , Mark H. Wilcoxson , Reza Sadjadi , Eric A. Hudson , James V. Tietz
IPC分类号： H01L21/00
CPC分类号： H01L21/31116 , H01L21/31138 , H01L21/76802 , H01L21/76829
摘要： A method for etching a feature in a low-k dielectric layer through a photoresist etch mask over a substrate. A gas-modulated cyclic stripping process is performed for more than three cycles for stripping a single photoresist mask. Each cycle of the gas-modulated cyclic stripping process comprises performing a protective layer formation phase and a stripping phase. The protective layer forming phase using first gas chemistry with a deposition gas chemistry, wherein the protective layer forming phase is performed in about 0.005 to 10 seconds for each cycle. The performing the stripping phase for stripping the photoresist mask using a second gas chemistry using a stripping gas chemistry, where the first gas chemistry is different than the second gas chemistry, wherein the etching phase is performed in about 0.005 to 10 seconds for each cycle.
摘要翻译：一种通过光刻胶蚀刻掩模在衬底上蚀刻低k电介质层中的特征的方法。执行气体调制的循环剥离工艺超过三个循环以剥离单个光致抗蚀剂掩模。气体调节循环汽提过程的每个循环包括进行保护层形成阶段和汽提阶段。使用具有沉积气化学性质的第一气体化学物质的保护层形成阶段，其中保护层形成阶段在每个循环中以约0.005至10秒钟进行。使用第二种气体化学法，使用剥离气体化学法，其中第一种气体化学物质与第二种气体化学物质不同，进行汽提阶段以剥离光致抗蚀剂掩模，其中每个循环在约0.005至10秒内进行蚀刻阶段。

42. 发明申请

US20070123053A1 Self-aligned pitch reduction 有权
标题翻译：自对准螺距减小
公开(公告)号：US20070123053A1
公开(公告)日：2007-05-31
申请号：US11291303
申请日：2005-11-30
申请人： Jisoo Kim , Sangheon Lee , Daehan Choi , S.M. Sadjadi
发明人： Jisoo Kim , Sangheon Lee , Daehan Choi , S.M. Sadjadi
IPC分类号： H01L21/302
CPC分类号： H01L21/0338
摘要： A method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The first set of dielectric layer features and the set of sacrificial layer features are filled with a filler material. The sacrificial layer is removed. The widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. A second set of dielectric layer features is etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
摘要翻译：提供了一种在电介质层中提供特征的方法。在电介质层上形成牺牲层。一组牺牲层特征被蚀刻到牺牲层中。通过牺牲层将介电层特征的第一组蚀刻到介电层中。第一组介电层特征和一组牺牲层特征用填充材料填充。牺牲层被去除。填充材料的各部分之间的间隙的宽度随收缩侧壁沉积而收缩。通过收缩侧壁沉积将第二组介电层特征蚀刻到介电层中。去除填充材料和收缩侧壁沉积。

43. 发明申请

US20070122977A1 SELF-ALIGNED PITCH REDUCTION 有权
标题翻译：自对准减法
公开(公告)号：US20070122977A1
公开(公告)日：2007-05-31
申请号：US11558238
申请日：2006-11-09
申请人： Ji Kim , Sangheon Lee , Daehan Choi , S. Sadjadi
发明人： Ji Kim , Sangheon Lee , Daehan Choi , S. Sadjadi
IPC分类号： H01L21/336
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/31144
摘要： A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features of the first set of sacrificial layer features are filled with filler material. The first sacrificial layer is removed. The spaces are shrunk with a shrink sidewall deposition. A second set of sacrificial layer features is etched into the second sacrificial layer. The filler material and shrink sidewall deposition are removed. A peripheral patterned mask is formed over the memory region and peripheral region. The second sacrificial layer is etched through the peripheral patterned mask. The peripheral patterned mask is removed. Features are etched into the etch layer from the second sacrificial layer.
摘要翻译：提供了一种用于在具有存储区域和周边区域的蚀刻层中提供特征的方法。存储器图案化掩模形成在第一牺牲层上。第一组牺牲层特征被蚀刻到第一牺牲层和第二牺牲层中。第一组牺牲层特征的特征填充有填充材料。第一牺牲层被去除。这些空间随着收缩侧壁沉积而收缩。第二组牺牲层特征被蚀刻到第二牺牲层中。去除填充材料和收缩侧壁沉积。在存储器区域和外围区域上形成周边图案化掩模。通过外围图案化掩模蚀刻第二牺牲层。去除周边图案掩模。特征从第二牺牲层蚀刻到蚀刻层中。

44. 发明授权

US07192531B1 In-situ plug fill 有权
标题翻译：现场插头填充
公开(公告)号：US07192531B1
公开(公告)日：2007-03-20
申请号：US10603412
申请日：2003-06-24
申请人： Sean S. Kang , Sangheon Lee , Wan-Lin Chen , Eric A. Hudson , Reza Sadjadi
发明人： Sean S. Kang , Sangheon Lee , Wan-Lin Chen , Eric A. Hudson , Reza Sadjadi
IPC分类号： H01L21/302
CPC分类号： H01L21/76808 , H01L21/31138
摘要： A method for forming damascene features in a dielectric layer over a barrier layer over a substrate is provided. A plurality of vias are etched in the dielectric layer to the barrier layer with a plasma etching process in the plasma processing chamber. A patterned photoresist layer is formed with a trench pattern. Within a single plasma process chamber a combination via plug deposition to form plugs in the vias over the barrier layer and trench etch is provided.
摘要翻译：提供了一种用于在衬底上的阻挡层上的介电层中形成镶嵌特征的方法。在等离子体处理室中通过等离子体蚀刻工艺将多个通孔在电介质层中蚀刻到阻挡层。形成具有沟槽图案的图案化的光致抗蚀剂层。在单个等离子体处理室内，提供了通过插塞沉积的组合以在阻挡层上的通孔中形成插塞和沟槽蚀刻。

45. 发明申请

US20060223327A1 Etch with photoresist mask 失效
标题翻译：刻蚀光刻胶掩模
公开(公告)号：US20060223327A1
公开(公告)日：2006-10-05
申请号：US11094559
申请日：2005-03-29
申请人： Jisoo Kim , Sangheon Lee , Binet Worsham , Robert Charatan , S.M. Sadjadi
发明人： Jisoo Kim , Sangheon Lee , Binet Worsham , Robert Charatan , S.M. Sadjadi
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31116
摘要： A method for etching a dielectric layer over a substrate is provided. A photoresist mask is formed over the dielectric layer. The substrate is placed in a plasma processing chamber. An etchant gas comprising NF3 is provided into the plasma chamber. A plasma is formed from the NF3 gas. The dielectric layer is etched through the photoresist mask with the plasma from the NF3 gas.
摘要翻译：提供了一种在衬底上蚀刻电介质层的方法。在电介质层上形成光致抗蚀剂掩模。将基板放置在等离子体处理室中。包含NF 3 N的蚀刻剂气体被提供到等离子体室中。从NF 3 N气体形成等离子体。通过来自NF 3 N 3气体的等离子体通过光致抗蚀剂掩模蚀刻电介质层。

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