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    • 3. 发明申请
    • Self-aligned pitch reduction
    • 自对准螺距减小
    • US20070123053A1
    • 2007-05-31
    • US11291303
    • 2005-11-30
    • Jisoo KimSangheon LeeDaehan ChoiS.M. Sadjadi
    • Jisoo KimSangheon LeeDaehan ChoiS.M. Sadjadi
    • H01L21/302
    • H01L21/0338
    • A method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The first set of dielectric layer features and the set of sacrificial layer features are filled with a filler material. The sacrificial layer is removed. The widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. A second set of dielectric layer features is etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
    • 提供了一种在电介质层中提供特征的方法。 在电介质层上形成牺牲层。 一组牺牲层特征被蚀刻到牺牲层中。 通过牺牲层将介电层特征的第一组蚀刻到介电层中。 第一组介电层特征和一组牺牲层特征用填充材料填充。 牺牲层被去除。 填充材料的各部分之间的间隙的宽度随收缩侧壁沉积而收缩。 通过收缩侧壁沉积将第二组介电层特征蚀刻到介电层中。 去除填充材料和收缩侧壁沉积。
    • 10. 发明申请
    • Methods for the optimization of substrate etching in a plasma processing system
    • 在等离子体处理系统中优化衬底蚀刻的方法
    • US20050205519A1
    • 2005-09-22
    • US10804430
    • 2004-03-19
    • Jisoo KimBinet WorshamBi-Ming YenPeter Loewenhardt
    • Jisoo KimBinet WorshamBi-Ming YenPeter Loewenhardt
    • B44C1/22C03C15/00C23F1/00H01L21/302H01L21/311H01L21/768
    • H01L21/31144H01L21/76811H01L21/76813
    • A method of etching a substrate in a plasma processing system is disclosed. The substrate has a semi-conductor layer, a first barrier layer disposed above the semi-conductor layer, a low-k layer disposed above the first barrier layer, a third hard mask layer disposed above the low-k layer; a second hard mask layer disposed above the third hard mask layer, and a first hard mask layer disposed above the second hard mask layer. The method includes alternatively etching the substrate with a first etchant and a second etchant, wherein the first etchant has a low selectivity to a first hard mask material of the first hard mask layer, a third hard mask material of the a third hard mask layer, and a first barrier layer material of the first barrier layer, but a high selectivity to a second hard mask material of the second hard mask layer; and wherein the second etchant has a high selectivity to the first hard mask material of the first hard mask layer, the third hard mask material of the third hard mask layer, and the first barrier layer material of the first barrier layer, and the first etchant has a low selectivity to the second hard mask material of the second hard mask layer.
    • 公开了一种在等离子体处理系统中蚀刻衬底的方法。 衬底具有半导体层,设置在半导体层上方的第一势垒层,设置在第一阻挡层上方的低k层,设置在低k层上方的第三硬掩模层; 设置在第三硬掩模层之上的第二硬掩模层,以及设置在第二硬掩模层上方的第一硬掩模层。 所述方法包括用第一蚀刻剂和第二蚀刻剂替代地蚀刻所述衬底,其中所述第一蚀刻剂对所述第一硬掩模层的第一硬掩模材料具有低选择性,所述第三硬掩模层的第三硬掩模材料, 和第一阻挡层的第一阻挡层材料,但对第二硬掩模层的第二硬掩模材料具有高选择性; 并且其中第二蚀刻剂对第一硬掩模层的第一硬掩模材料,第三硬掩模层的第三硬掩模材料和第一阻挡层的第一阻挡层材料和第一蚀刻剂具有高选择性 对第二硬掩模层的第二硬掩模材料具有低选择性。