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41. 发明申请

US20080305760A1 Envelope Detector for AM Radio 失效
标题翻译： AM无线电信封检测器
公开(公告)号：US20080305760A1
公开(公告)日：2008-12-11
申请号：US11760227
申请日：2007-06-08
申请人： David Meltzer , Gregory Blum
发明人： David Meltzer , Gregory Blum
IPC分类号： H04B1/16
CPC分类号： H03D1/18 , H04B1/123
摘要： A receiver for receiving an amplitude modulated (AM) signal may include a first and a second detector for detecting the maximum and minimum envelope values, respectively, of the received AM signal and an equalizer for periodically equalizing the maximum and minimum envelope values. A method for receiving an AM signal may include unidirectionally increasing a first output signal up to the maximum envelope value, unidirectionally decreasing a second output signal down to the minimum envelope value, and periodically equalizing the first and the second output signals.
摘要翻译：用于接收幅度调制（AM）信号的接收机可以包括第一和第二检测器，用于分别检测所接收的AM信号的最大和最小包络值，以及用于周期性均衡最大和最小包络值的均衡器。用于接收AM信号的方法可以包括将第一输出信号单向增加直到最大包络值，将第二输出信号单向地减小到最小包络值，并周期性均衡第一和第二输出信号。

42. 发明授权

US07356673B2 System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form 有权
标题翻译：系统和方法包括用于以预解码形式存储频繁执行的指令的分布式指令缓冲器
公开(公告)号：US07356673B2
公开(公告)日：2008-04-08
申请号：US09845693
申请日：2001-04-30
申请人： Erik R. Altman , Clair John Glossner, III , Erdem Hokenek , David Meltzer , Mayan Moudgill
发明人： Erik R. Altman , Clair John Glossner, III , Erdem Hokenek , David Meltzer , Mayan Moudgill
IPC分类号： G06F9/30 , G06F9/45
CPC分类号： G06F9/3802 , G06F9/3867 , G06F9/3885
摘要： A system and method is provided for processing a first instruction set and a second instruction set in a single processor. The method includes storing a plurality of instructions of the second instruction set in a plurality of buffers proximate to a plurality of execution units, executing an instruction of the first instruction set in response to a first counter, and executing at least one instruction of the second instruction set in response to at least a second counter, wherein the second counter is invoked by a branch instruction of the first instruction set.
摘要翻译：提供了一种用于在单个处理器中处理第一指令集和第二指令集的系统和方法。该方法包括将第二指令集的多个指令存储在靠近多个执行单元的多个缓冲器中，响应于第一计数器执行第一指令集的指令，并且执行第二指令集的至少一个指令指令响应于至少第二计数器设置，其中所述第二计数器由所述第一指令集的分支指令调用。

43. 发明授权

US07268645B2 Integrated resonator structure and methods for its manufacture and use 有权
标题翻译：集成谐振器结构及其制造和使用的方法
公开(公告)号：US07268645B2
公开(公告)日：2007-09-11
申请号：US11125378
申请日：2005-05-09
申请人： David Meltzer , Michael Hargrove
发明人： David Meltzer , Michael Hargrove
IPC分类号： H03H7/00 , H03H7/01
CPC分类号： H01L28/10 , H01F17/0013 , H03H2001/0064
摘要： An improved integrated LC resonator and methods for making and using the same are disclosed. The resonator includes (i) a first capacitor plate; (ii) an inductor over and in electrical communication with the first capacitor plate; and (iii) a second capacitor plate over and in electrical communication with the inductor. The method of making includes sequentially forming a first capacitor plate, a first dielectric layer thereon, a first via and an inductor, a second dielectric layer on the inductor, and a second via and a second capacitor plate. Each of the capacitor plates and the inductor are generally formed in different integrated circuit layers (for example, different metallization layers). Embodiments of the present invention can advantageously provide an integrated LC resonator tank having: (i) relatively high Q by reducing or minimizing parasitic effects; and (ii) relatively high shielding from the semiconductor substrate.
摘要翻译：公开了一种改进的集成LC谐振器及其制造和使用方法。谐振器包括（i）第一电容器板; （ii）与所述第一电容器板电连接的电感器; 和（iii）在电感器上并与电感器电连通的第二电容器板。制造方法包括依次形成第一电容器板，第一电介质层，第一通孔和电感器，电感器上的第二电介质层，以及第二通孔和第二电容器板。每个电容器板和电感器通常形成在不同的集成电路层（例如，不同的金属化层）中。本发明的实施例可以有利地提供一种集成的LC谐振器箱，其具有：（i）通过减小或最小化寄生效应来实现相对较高的Q; 和（ii）与半导体衬底相对较高的屏蔽。

44. 发明授权

US07265635B2 Method and apparatus for assisting pull-in of a phase-locked loop 失效
标题翻译：用于辅助锁相环的拉入的方法和装置
公开(公告)号：US07265635B2
公开(公告)日：2007-09-04
申请号：US11212233
申请日：2005-08-26
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0891 , H04L7/033
摘要： A method, algorithm, software, architecture, circuit, and/or system for assisting pull-in of a phase-locked loop (PLL) are disclosed. In one embodiment, a PLL can include: (i) a phase detector that may receive a serial data stream and output a pump control signal; (ii) a charge pump that can receive the pump control signal and substantially determine a frequency control when a precharge signal is de-asserted; (iii) a precharge/filter circuit that may connect to the charge pump and may substantially determine the frequency control when the precharge signal is asserted; and (iv) an oscillator that may connect to the precharge/filter circuit and may provide a recovered clock in response to the frequency control, where the recovered clock may be correlated to a frequency of the serial data stream. The frequency control may be current and/or voltage based, for example. Embodiments of the present invention can advantageously provide a reliable and simplified design approach for pulling-in a PLL lock.
摘要翻译：公开了一种用于辅助锁相环（PLL）的拉入的方法，算法，软件，架构，电路和/或系统。在一个实施例中，PLL可以包括：（i）相位检测器，其可以接收串行数据流并输出泵控制信号; （ii）电荷泵，其能够接收泵控制信号并且在预充电信号被取消断言时基本上确定频率控制; （iii）预充电/滤波电路，其可以连接到电荷泵，并且可以在预充电信号被断言时基本上确定频率控制; 以及（iv）可以连接到预充电/滤波器电路并且可以响应于频率控制提供恢复的时钟的振荡器，其中恢复的时钟可以与串行数据流的频率相关联。例如，频率控制可以是电流和/或电压。本发明的实施例可以有利地提供用于拉入PLL锁的可靠和简化的设计方法。

45. 发明授权

US07212050B2 System and method for synthesizing a clock at digital wrapper (FEC) and base frequencies using one precision resonator 有权
标题翻译：使用一个精密谐振器在数字封装（FEC）和基频合成时钟的系统和方法
公开(公告)号：US07212050B2
公开(公告)日：2007-05-01
申请号：US11016314
申请日：2004-12-17
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03L7/06
CPC分类号： H03L7/099 , H03L7/0812 , H03L7/0891 , H03L7/183 , H03L7/23
摘要： A precision PLL based transceiver having a single precision SAW or crystal resonator is configured to lock onto multiple different input frequencies and output generated clocks at the multiple different frequencies. The input reference frequency may be higher or lower than the resonator frequency. A fraction of two whole numbers describing a ratio of the resonator frequency to a given input frequency reference is first obtained. One of the numerator or denominator in the fraction is used to set the divide value of a first frequency divider coupling a VFO based on the resonator to a feedback input on a PFD. The other of the numerator or denominator is used to set a second frequency divider coupling the input frequency reference signal to the PFD. A first frequency multiplier is given a multiplication factor matching the divide value of the second frequency divider, and used to couple the output of the first frequency divider to the output of the PLL. Alternatively, a second frequency divider may be inserted between the reference frequency input and the PFD to match the frequency, or a multiple thereof, of the VFO output, which may bypass the first frequency divider in the feedback path to the PFD.
摘要翻译：具有单精度SAW或晶体谐振器的精密PLL收发器配置成锁定在多个不同的输入频率上，并以多个不同的频率输出产生的时钟。输入参考频率可以高于或低于谐振器频率。首先获得描述谐振器频率与给定输入频率参考值的比率的两个整数的一部分。分数中的分子或分母之一用于将基于谐振器的VFO的第一分频器的分频值设置为PFD上的反馈输入。分子或分母中的另一个用于设置将输入频率参考信号耦合到PFD的第二分频器。第一倍频器被给予与第二分频器的分频匹配的乘法因子，并且用于将第一分频器的输出耦合到PLL的输出。或者，可以在参考频率输入和PFD之间插入第二分频器以匹配可以绕过PFD的反馈路径中的第一分频器的VFO输出的频率或其倍数。

46. 发明授权

US07187222B2 CMOS master/slave flip-flop with integrated multiplexor 失效
标题翻译：具有集成多路复用器的CMOS主/从触发器
公开(公告)号：US07187222B2
公开(公告)日：2007-03-06
申请号：US11016430
申请日：2004-12-17
申请人： David Meltzer , Muralikumar A. Padaparambil
发明人： David Meltzer , Muralikumar A. Padaparambil
IPC分类号： H03K3/289
CPC分类号： H03K3/356139
摘要： A CML master-slave latch incorporates logic into its master latching circuitry to incorporate a multiplexing function into the flip-flop. The multiplexing logic makes use of the pull-up loads and current source of the master latching circuitry. In this manner the pull-up loads and current source typically required for a stand-alone multiplexor are eliminated. Subsequently, the size of the present hybrid master-slave latch is smaller and consumes less power than a traditional combination of an independent multiplexor and master-slave latch. Since the master latching circuitry feeds only into the slave latching circuitry, the pull-up loads and the current sources of the master latching circuitry and slave latching circuitry may be optimized separately for achieving faster performance or less power consumption.
摘要翻译： CML主从锁存器将逻辑并入其主锁存电路，以将多路复用功能并入到触发器中。复用逻辑利用主锁存电路的上拉负载和电流源。以这种方式，消除了独立复用器通常需要的上拉负载和电流源。随后，当前的混合主 - 从锁存器的大小比独立多路复用器和主 - 从锁存器的传统组合消耗更少的功率。由于主锁存电路仅馈入从锁存电路，因此可以单独优化主锁存电路和从锁存电路的上拉负载和电流源，以实现更快的性能或更低的功耗。

47. 发明授权

US07167058B2 Temperature compensation for a variable frequency oscillator without reducing pull range 失效
标题翻译：可变频率振荡器的温度补偿，不减小拉范围
公开(公告)号：US07167058B2
公开(公告)日：2007-01-23
申请号：US10733094
申请日：2003-12-11
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03B1/00
CPC分类号： H03L1/022 , H03B5/04 , H03L1/023 , H03L7/00 , Y10S331/03
摘要： A variable frequency oscillator having multiple, independent frequency control inputs, each coupled to a respective tuning sub-circuit. The tuning sub-circuits are connected in parallel with each other and with a resonator module, which may be a quartz crystal, inductor, or other reactance component. Each tuning sub-circuit consists of two varactors with their respective cathodes coupled to each other and to their corresponding frequency control input. By having the tuning sub-circuits connected in parallel to the resonator, the overall frequency pull range of each frequency control input remains unaffected by the activation of any other frequency control input. Preferably, at least one frequency control input is a temperature compensation control input that can maintain the variable oscillator insensitive to temperature variations while the remaining frequency control inputs provide functional frequency control.
摘要翻译：具有多个独立频率控制输入的可变频率振荡器，每个都耦合到相应的调谐子电路。调谐子电路彼此并联并且具有可以是石英晶体，电感器或其它电抗分量的谐振器模块。每个调谐子电路由两个变容二极管组成，它们各自的阴极相互耦合并连接到它们对应的频率控制输入端。通过使调谐子电路与谐振器并联连接，每个频率控制输入的总频率拉动范围不受任何其它频率控制输入的激活的影响。优选地，至少一个频率控制输入是温度补偿控制输入，其可以保持可变振荡器对温度变化不敏感，而剩余频率控制输入提供功能频率控制。

48. 发明授权

US07157942B2 Digital frequency difference detector with inherent low pass filtering and lock detection 有权
标题翻译：数字频差检测器，具有固有的低通滤波和锁定检测
公开(公告)号：US07157942B2
公开(公告)日：2007-01-02
申请号：US11007546
申请日：2004-12-08
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03D3/24 , H03D13/00
CPC分类号： H03L7/085 , H03D13/002 , H03L7/095
摘要： A structure and method for implementing a fully digital frequency difference detector uses an n-bit counter to count cycles of a reference clock signal and an m-bit counter to count cycles of a synthesized clock signal, where m is greater than n. The two counters operate concurrently, and both are halted when the n-bit counter overflows into its nth bit position. Two latches respectively record if bits n and (n+1) in the m-bit become set prior to the n-bit counter overflowing. By observing the state of the two latches and the state of a predefined bit range within the m-counter, the frequency difference detector can determined if the frequency of the synthesized clock is greater than, less than, or locked to the frequency of the reference clock signal.
摘要翻译：用于实现全数字频差检测器的结构和方法使用n位计数器对参考时钟信号和m位计数器的周期进行计数，以计数合成时钟信号的周期，其中m大于n。两个计数器同时运行，当n位计数器溢出到其第n个位位置时，两个计数器都停止。两个锁存器分别记录在n位计数器溢出之前m位中的位n和（n + 1）是否被置位。通过观察两个锁存器的状态和m个计数器内的预定义位范围的状态，频率差检测器可以确定合成时钟的频率是否大于，小于或锁定到参考的频率时钟信号。

49. 发明授权

US07082178B2 Lock detector circuit for dejitter phase lock loop (PLL) 失效
公开(公告)号：US07082178B2
公开(公告)日：2006-07-25
申请号：US10016915
申请日：2001-12-14
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03D3/24
CPC分类号： H03L7/0891 , H03L7/095 , Y10S331/02
摘要： A phase lock loop lock detect circuit determines whether an output signal of the phase lock loop is in phase-frequency synchronization with an input reference timing signal and provides an unlock alarm signal indicating that the output signal of a phase lock loop is no longer in phase-frequency synchronization with an input reference timing signal. The lock detection circuit has a first logic function circuit to combine a frequency increase signal and a frequency decrease signal of said phase lock loop to provide a frequency deviation signal. The first logic function in the preferred embodiment of this invention is an OR gate. The output of the first logic function circuit is an input to a second logic function circuit. The second logic function circuit combines the frequency deviation signal with the input reference signal, which is applied to a second input of the second logic function, to determine that the frequency deviation signal has a greater duration than a portion of a cycle of said input reference signal and provide an unlock alarm signal. The second logic function circuit in the preferred embodiment of this invention is an AND gate. The lock detection circuit further includes a latching circuit in communication with the second logic function and the input reference signal to capture and retain said unlock alarm signal indicating loss of phase-frequency lock of said phase lock loop.

50. 发明授权

US07034594B2 Differential master/slave CML latch 失效
标题翻译：差分主/从CML锁存器
公开(公告)号：US07034594B2
公开(公告)日：2006-04-25
申请号：US10833605
申请日：2004-04-28
申请人： David Meltzer , Muralikumar A. Padaparambil , Tat C. Wu
发明人： David Meltzer , Muralikumar A. Padaparambil , Tat C. Wu
IPC分类号： H03K3/037
CPC分类号： H03K3/356139 , H03K3/3562
摘要： A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.
摘要翻译：全差分相位和频率检测器利用多功能差分逻辑门来实现差分和门操作，并提供完全差分D触发器。多功能差分逻辑门有四个输入，可以分为两对真和补两个信号。通过选择性地将输入重新分配给不同的信号对，可以使差分逻辑门提供同时的与/或非逻辑运算或同时的OR / NOR逻辑运算之一。差分D-触发器按照主/从配置实现，并且响应于输入时钟信号，输入复位输入和输入数据信号的真实和补码形式，并且还提供输出的真实和补充形式信号。相位和频率检测器中的所有组件都以CML电路配置为例。

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