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41. 发明授权

US08116127B2 Phase change memory devices and systems, and related programming methods 有权
标题翻译：相变存储器件和系统以及相关编程方法
公开(公告)号：US08116127B2
公开(公告)日：2012-02-14
申请号：US12559792
申请日：2009-09-15
申请人： Woo-Yeong Cho , Kwang-Jin Lee , Hye-Jin Kim
发明人： Woo-Yeong Cho , Kwang-Jin Lee , Hye-Jin Kim
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0076 , G11C2013/0078
摘要： A method of writing data in a phase change memory includes receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells, sensing data stored in the selected phase change memory cell, determining whether or not the sensed data is equal to the write data, and if the sensed data is not equal to the write data, iteratively applying a write current to the selected phase change memory cell, wherein a resistance state of the phase change memory cell is changed by heat corresponding to a level of the write current, and the level of the write current is changed between successive iterative applications.
摘要翻译：在相变存储器中写入数据的方法包括：接收要写入多个相变存储单元中的选定相变存储单元的写入数据，感测存储在所选择的相变存储单元中的数据，确定是否感测到数据等于写入数据，并且如果感测到的数据不等于写入数据，则向所选择的相变存储器单元迭代地施加写入电流，其中相变存储单元的电阻状态由对应于写入电流的电平和写入电流的电平在连续的迭代应用程序之间改变。

42. 发明授权

US07994493B2 Phase change memory devices employing cell diodes and methods of fabricating the same 有权
标题翻译：使用单元二极管的相变存储器件及其制造方法
公开(公告)号：US07994493B2
公开(公告)日：2011-08-09
申请号：US12196137
申请日：2008-08-21
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L29/04 , H01L47/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.
摘要翻译：相变存储器件可以包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线。字线可以具有不同于第一导电类型和基本上平坦的顶表面的第二导电类型。第一和第二半导体图案可以顺序地堆叠在每个字线上，并且可以提供绝缘层以填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体图案之间的间隙区域。多个相变材料图案可以二维排列在绝缘层上并电连接到第二半导体图案。

43. 发明申请

US20110188303A1 Phase change memory device generating program current and mehtod thereof 有权
标题翻译：相变存储器件产生程序电流和电流
公开(公告)号：US20110188303A1
公开(公告)日：2011-08-04
申请号：US13064672
申请日：2011-04-07
申请人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
发明人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.
摘要翻译：相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。存储单元阵列可以包括多个存储单元。写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

44. 发明申请

US20110170332A1 Methods of Driving Nonvolatile Memory Devices that Utilize Read/Write Merge Circuits 审中-公开
标题翻译：驱动使用读/写合并电路的非易失性存储器件的方法
公开(公告)号：US20110170332A1
公开(公告)日：2011-07-14
申请号：US13011188
申请日：2011-01-21
申请人： Hyung-rok Oh , Sang-beom Kang , Woo-yeong Cho , Joon-min Park
发明人： Hyung-rok Oh , Sang-beom Kang , Woo-yeong Cho , Joon-min Park
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/12 , G11C5/145 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/003 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79
摘要： An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.
摘要翻译：集成电路存储器件包括具有电耦合到其中的存储器单元的第一多个线的非易失性存储器单元阵列（例如，可变电阻单元）。提供读/写控制电路。读/写控制电路包括读/写合并电路和列选择电路。被配置为在相应的写入和读取操作期间以不相等的写入和读取电压驱动所述第一多个线路中的所选择的一个线路的所述读取/写入控制电路包括补偿单元。该补偿单元被配置为在读取操作期间向第一多个线路电路中的所选择的一个电路提供读取补偿电流。

45. 发明授权

US07961508B2 Phase-change random access memory 有权
标题翻译：相变随机存取存储器
公开(公告)号：US07961508B2
公开(公告)日：2011-06-14
申请号：US12771028
申请日：2010-04-30
申请人： Byung-Gil Choi , Du-Eung Kim , Woo-Yeong Cho , Hye-Jin Kim
发明人： Byung-Gil Choi , Du-Eung Kim , Woo-Yeong Cho , Hye-Jin Kim
IPC分类号： G11C11/00
CPC分类号： G11C29/808 , G11C29/02 , G11C29/027 , G11C29/787 , G11C29/804 , G11C29/846
摘要： A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.
摘要翻译：相变随机存取存储器包括存储块，该存储块包括对应于同一列地址的多个存储器列并使用不同的输入/输出路径; 冗余存储器块，其包括使用不同的输入/输出路径的多个冗余存储器列; 以及输入/输出控制器，其使用所述多个冗余存储器列中的至少一个来修复所述多个存储器列中的至少一个，并且响应于输入/输出修复模式来控制使用冗余存储器列同时修复的存储器列的数量控制信号。

46. 发明授权

US07936612B2 Phase change memory device generating program current and method thereof 有权
标题翻译：相变存储器件产生程序电流及其方法
公开(公告)号：US07936612B2
公开(公告)日：2011-05-03
申请号：US12654338
申请日：2009-12-17
申请人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
发明人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.
摘要翻译：相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。存储单元阵列可以包括多个存储单元。写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

47. 发明申请

US20110063904A1 PHASE CHANGE MEMORY DEVICE, MEMORY SYSTEM, AND PROGRAMMING METHOD 有权
标题翻译：相变存储器件，存储器系统和编程方法
公开(公告)号：US20110063904A1
公开(公告)日：2011-03-17
申请号：US12879157
申请日：2010-09-10
申请人： Sang-Hoan CHANG , Seong-Moo HEO , Kwang-Suk YU , Yeong-Taek LEE , Woo-Yeong CHO
发明人： Sang-Hoan CHANG , Seong-Moo HEO , Kwang-Suk YU , Yeong-Taek LEE , Woo-Yeong CHO
IPC分类号： G11C11/21 , G11C7/06 , G11C7/10 , G11C7/12
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0057 , G11C2013/0092 , G11C2213/56
摘要： A method of programming a phase change memory device is disclosed. Write data is programmed in a plurality of phase change memory cells by applying write pulses to each of the plurality of phase change memory cells. Whether each of the phase change memory cells is programmed is verified by applying at least one verification pulse to each of the phase-change memory cells. A number of applications for the at least one verification pulse and the intervals between respective applications of the at least one verification pulse are varied in accordance with a verification result for each of the phase-change memory cells.
摘要翻译：公开了一种编程相变存储器件的方法。通过向多个相变存储单元中的每一个施加写脉冲，将写数据编程在多个相变存储单元中。通过对每个相变存储单元施加至少一个验证脉冲来验证每个相变存储器单元是否被编程。至少一个验证脉冲的应用程序和至少一个验证脉冲的相应应用之间的间隔的数量根据每个相变存储单元的验证结果而变化。

48. 发明申请

US20110053293A1 MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：磁记忆体装置及其制造方法
公开(公告)号：US20110053293A1
公开(公告)日：2011-03-03
申请号：US12915335
申请日：2010-10-29
申请人： Woo-Yeong CHO , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
发明人： Woo-Yeong CHO , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
IPC分类号： H01L21/62
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

49. 发明授权

US07894236B2 Nonvolatile memory devices that utilize read/write merge circuits 失效
标题翻译：使用读/写合并电路的非易失性存储器件
公开(公告)号：US07894236B2
公开(公告)日：2011-02-22
申请号：US11945443
申请日：2007-11-27
申请人： Hyung-rok Oh , Woo-yeong Cho , Sang-beom Kang , Joon-min Park
发明人： Hyung-rok Oh , Woo-yeong Cho , Sang-beom Kang , Joon-min Park
IPC分类号： G11C7/00 , G11C7/12
CPC分类号： G11C7/12 , G11C5/145 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/003 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79
摘要： An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.
摘要翻译：集成电路存储器件包括具有电耦合到其中的存储器单元的第一多个线的非易失性存储器单元阵列（例如，可变电阻单元）。提供读/写控制电路。读/写控制电路包括读/写合并电路和列选择电路。被配置为在相应的写入和读取操作期间以不相等的写入和读取电压驱动所述第一多个线路中的所选择的一个线路的所述读取/写入控制电路包括补偿单元。该补偿单元被配置为在读取操作期间向第一多个线路电路中的所选择的一个电路提供读取补偿电流。

50. 发明申请

US20110002160A1 METHOD OF OPERATING A MAGNETORESISTIVE RAM 失效
标题翻译：操作磁记录RAM的方法
公开(公告)号：US20110002160A1
公开(公告)日：2011-01-06
申请号：US12875297
申请日：2010-09-03
申请人： Woo-yeong CHO , Yun-seung SHIN
发明人： Woo-yeong CHO , Yun-seung SHIN
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1655 , G11C11/1659 , Y10S977/935
摘要： A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.
摘要翻译：磁阻随机存取存储器（RAM）可以包括多个可变电阻器件，电连接到相应的可变电阻器件的多个读位线以及与读位线交替的多个写位线。磁阻RAM可以被配置为当向第一可变电阻器件写入第一数据时，通过与第一可变电阻器件相邻的第一写入位线施加第一写入电流，并且将第一写入电流施加到与第一可写入位置相邻的第二写入位置第二可变电阻器件，第二可变电阻器件与第一写入位线相邻，第一写入位线和第二写入位线之间以及第一写入电流和第一抑制电流沿相同的方向流动。

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