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1. 发明授权

US6157590A Solid state memory having a latch circuit 有权
标题翻译：具有锁存电路的固态存储器
公开(公告)号：US6157590A
公开(公告)日：2000-12-05
申请号：US404143
申请日：1999-09-27
申请人： Sang Hoan Chang
发明人： Sang Hoan Chang
IPC分类号： G11C16/06 , G11C5/06 , G11C8/00
CPC分类号： G11C8/00 , G11C5/066
摘要： A solid state memory according to the present invention comprises a plurality of memory chips; a confirmation circuit to confirm an input address by comparing said input address to each address latched to a latch circuit; a common serial bus for transmitting commands, addresses and data between the memory chips and the confirmation circuit; and a printed circuit board on which the memory chips and the confirmation circuit are mounted.
摘要翻译：根据本发明的固态存储器包括多个存储器芯片; 确认电路，用于通过将所述输入地址与锁存到锁存电路的每个地址进行比较来确认输入地址; 用于在存储器芯片和确认电路之间发送命令，地址和数据的公共串行总线; 以及安装有存储芯片和确认电路的印刷电路板。

2. 发明授权

US08279664B2 Phase change memory device, memory system, and programming method using variable verification pulses 有权
标题翻译：相变存储器件，存储器系统和使用可变校验脉冲的编程方法
公开(公告)号：US08279664B2
公开(公告)日：2012-10-02
申请号：US12879157
申请日：2010-09-10
申请人： Sang-Hoan Chang , Seong-Moo Heo , Kwang-Suk Yu , Yeong-Taek Lee , Woo-Yeong Cho
发明人： Sang-Hoan Chang , Seong-Moo Heo , Kwang-Suk Yu , Yeong-Taek Lee , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0057 , G11C2013/0092 , G11C2213/56
摘要： In a method of programming a phase change memory device, write data is programmed in a plurality of phase change memory cells by applying write pulses to each of the plurality of phase change memory cells. Whether each of the phase change memory cells is programmed is verified by applying verification pulses to each of the phase-change memory cells. A number of applications for the verification pulses and the intervals between respective applications of the verification pulses are varied in accordance with a verification result for each of the phase-change memory cells.
摘要翻译：在对相变存储器件进行编程的方法中，通过向多个相变存储器单元中的每一个施加写脉冲，将写数据编程在多个相变存储器单元中。通过将验证脉冲应用于每个相变存储单元来验证每个相变存储单元是否被编程。用于验证脉冲的多个应用以及验证脉冲的相应应用之间的间隔根据每个相变存储单元的验证结果而变化。

3. 发明申请

US20120087183A1 METHODS OF OPERATING PRAMS USING INITIAL PROGRAMMED RESISTANCES AND PRAMS USING THE SAME 有权
标题翻译：使用初始编程电阻和PRAMS操作的方法
公开(公告)号：US20120087183A1
公开(公告)日：2012-04-12
申请号：US13168553
申请日：2011-06-24
申请人： Sang Hoan Chang
发明人： Sang Hoan Chang
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0007 , G11C13/0033
摘要： A method of operating a PRAM device can be provided by reading a PRAM reference cell to determine an initial programmed resistance of the PRAM reference cell and determining whether the initial programmed resistance has been reduced to below a predetermined reference threshold resistance.
摘要翻译：可以通过读取PRAM参考单元来确定PRAM参考单元的初始编程电阻并确定初始编程电阻是否已经降低到低于预定参考阈值电阻，来提供操作PRAM器件的方法。

4. 发明授权

US06821850B2 Method of manufacturing a multi-level flash EEPROM cell 失效
标题翻译：制造多级闪存EEPROM单元的方法
公开(公告)号：US06821850B2
公开(公告)日：2004-11-23
申请号：US10627917
申请日：2003-07-28
申请人： Sang-Hoan Chang , Ki-Seog Kim , Keun-Woo Lee , Sung-Kee Park
发明人： Sang-Hoan Chang , Ki-Seog Kim , Keun-Woo Lee , Sung-Kee Park
IPC分类号： H02L21336
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/0425 , G11C2211/5611
摘要： A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.
摘要翻译：提供多级EEPROM单元及其制造方法，以改善多电平单元的程序特性。为此，多级闪速EEPROM单元包括浮置栅极，其通过下面的隧道氧化物层与硅衬底电隔离，形成在浮置栅极的顶部上的第一电介质层，形成在第一控制栅极上的第一控制栅极所述浮置栅极通过所述第一介电层与所述浮置栅极电分离，形成在所述第一控制栅极的侧壁和顶部上的第二介电层，形成在所述第一控制栅极的侧壁和顶部上的第二控制栅极为通过第二电介质层与第一控制栅极电分离，以及在衬底中形成的与第二控制栅极的两个边缘自对准的源极和漏极。

5. 发明授权

US06391665B1 Method of monitoring a source contact in a flash memory 有权
标题翻译：监视闪存中的源触点的方法
公开(公告)号：US06391665B1
公开(公告)日：2002-05-21
申请号：US09722112
申请日：2000-11-27
申请人： Sang Hoan Chang , Ki Seog Kim , Jin Shin , Keun Woo Lee
发明人： Sang Hoan Chang , Ki Seog Kim , Jin Shin , Keun Woo Lee
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , G11C16/04 , G11C29/50 , G11C29/50008 , G11C2029/5006 , H01L21/76895 , H01L27/115
摘要： There is disclosed a method of monitoring a source contact in a flash memory by which whether a source contact having a narrow contact area contacts or not can be easily monitored using over-erase cell characteristic in a flash cell, in a flash memory device in which a source line is formed by a local interconnection method. In the present invention, in order to monitor a contact state at source contacts, the same voltage to the erase condition of a cell is applied to respective terminals (VG terminal, VD terminal, VS terminal and VSS terminal) wherein all the electrons existing at a floating gate in all the cells connected to the VS terminal and VSS terminal become turned on so that they can be over-erased. On the other hands, as electrons existing at the floating gate in two cells shared by any source contacts having a defect contact are not erased, the cells remain turn-off. In this state, if test voltages (VG=0V, VD
摘要翻译：公开了一种监视闪速存储器中的源极触点的方法，通过该闪光存储器中的源极触点可以容易地利用闪存单元中的过擦除单元特性来容易地监视具有窄接触区域的源极触点的触点，源线由本地互连方式形成。在本发明中，为了监测源极触点的接触状态，将与电池的擦除状态相同的电压施加到各个端子（VG端子，VD端子，VS端子和VSS端子），其中所有电子存在于连接到VS端子和VSS端子的所有单元中的浮动栅极变为导通，使得它们可能被过擦除。另一方面，由于存在于由具有缺陷接触的任何源极触点共享的两个电池中的浮动栅极处的电子不被擦除，所以电池保持关断。在这种状态下，如果施加了测试电压（VG = 0V，VD <5V，VS =浮动，VSS =接地），则在具有接触缺陷的部分中，从VD端子到VSS端子的电流断开，从而允许要监控的源触点的接触状态。

6. 发明授权

US09087220B2 Nonvolatile memory cell with authentication key storage 有权
标题翻译：具有认证密钥存储的非易失性存储单元
公开(公告)号：US09087220B2
公开(公告)日：2015-07-21
申请号：US13450578
申请日：2012-04-19
申请人： Sang Hoan Chang , Kwang Jin Lee
发明人： Sang Hoan Chang , Kwang Jin Lee
IPC分类号： G06F21/79
CPC分类号： G06F21/79 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： A nonvolatile memory device includes a memory cell array configured to store an authentication key and authentication key configuration information in first and second pluralities of nonvolatile memory cells, along with data whose security is to be protected, and a control circuit controlling an operation of the memory cell array.
摘要翻译：非易失性存储器件包括：存储单元阵列，被配置为将第一和第二多个非易失性存储器单元中的认证密钥和认证密钥配置信息与安全性要保护的数据一起存储;以及控制电路，用于控制存储器的操作单元格阵列。

7. 发明授权

US08830724B2 Methods of operating PRAMS using initial programmed resistances and PRAMS using the same 有权
标题翻译：使用初始编程电阻运行PRAMS的方法和使用其的PRAMS
公开(公告)号：US08830724B2
公开(公告)日：2014-09-09
申请号：US13168553
申请日：2011-06-24
申请人： Sang Hoan Chang
发明人： Sang Hoan Chang
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0007 , G11C13/0033
摘要： A method of operating a PRAM device includes reading a PRAM reference cell to determine an initial programmed resistance of the PRAM reference cell and determining whether the initial programmed resistance has been reduced to below a predetermined reference threshold resistance.
摘要翻译：一种操作PRAM设备的方法包括读取PRAM参考单元以确定PRAM参考单元的初始编程电阻并确定初始编程电阻是否已经降低到低于预定参考阈值电阻。

8. 发明申请

US20130014269A1 NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：非易失性存储器件和包括其的存储器系统
公开(公告)号：US20130014269A1
公开(公告)日：2013-01-10
申请号：US13450578
申请日：2012-04-19
申请人： Sang Hoan Chang , Kwang Jin Lee
发明人： Sang Hoan Chang , Kwang Jin Lee
IPC分类号： G06F21/00
CPC分类号： G06F21/79 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： A nonvolatile memory device includes a memory cell array configured to store an authentication key and authentication key configuration information in first and second pluralities of nonvolatile memory cells, along with data whose security is to be protected, and a control circuit controlling an operation of the memory cell array.
摘要翻译：非易失性存储器件包括：存储单元阵列，被配置为将第一和第二多个非易失性存储器单元中的认证密钥和认证密钥配置信息与安全性要保护的数据一起存储;以及控制电路，用于控制存储器的操作单元格阵列。

9. 发明申请

US20110063904A1 PHASE CHANGE MEMORY DEVICE, MEMORY SYSTEM, AND PROGRAMMING METHOD 有权
标题翻译：相变存储器件，存储器系统和编程方法
公开(公告)号：US20110063904A1
公开(公告)日：2011-03-17
申请号：US12879157
申请日：2010-09-10
申请人： Sang-Hoan CHANG , Seong-Moo HEO , Kwang-Suk YU , Yeong-Taek LEE , Woo-Yeong CHO
发明人： Sang-Hoan CHANG , Seong-Moo HEO , Kwang-Suk YU , Yeong-Taek LEE , Woo-Yeong CHO
IPC分类号： G11C11/21 , G11C7/06 , G11C7/10 , G11C7/12
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0057 , G11C2013/0092 , G11C2213/56
摘要： A method of programming a phase change memory device is disclosed. Write data is programmed in a plurality of phase change memory cells by applying write pulses to each of the plurality of phase change memory cells. Whether each of the phase change memory cells is programmed is verified by applying at least one verification pulse to each of the phase-change memory cells. A number of applications for the at least one verification pulse and the intervals between respective applications of the at least one verification pulse are varied in accordance with a verification result for each of the phase-change memory cells.
摘要翻译：公开了一种编程相变存储器件的方法。通过向多个相变存储单元中的每一个施加写脉冲，将写数据编程在多个相变存储单元中。通过对每个相变存储单元施加至少一个验证脉冲来验证每个相变存储器单元是否被编程。至少一个验证脉冲的应用程序和至少一个验证脉冲的相应应用之间的间隔的数量根据每个相变存储单元的验证结果而变化。

10. 发明授权

US06630709B2 Multi-level flash EEPROM cell and method of manufacture thereof 失效
标题翻译：多级闪存EEPROM单元及其制造方法
公开(公告)号：US06630709B2
公开(公告)日：2003-10-07
申请号：US09739401
申请日：2000-12-19
申请人： Sang-Hoan Chang , Ki-Seog Kim , Keun-Woo Lee , Sung-Kee Park
发明人： Sang-Hoan Chang , Ki-Seog Kim , Keun-Woo Lee , Sung-Kee Park
IPC分类号： H01L2976
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/0425 , G11C2211/5611
摘要： A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.
摘要翻译：提供多级EEPROM单元及其制造方法，以改善多电平单元的程序特性。为此，多级闪速EEPROM单元包括浮置栅极，其通过下面的隧道氧化物层与硅衬底电隔离，形成在浮置栅极的顶部上的第一电介质层，形成在第一控制栅极上的第一控制栅极所述浮置栅极通过所述第一介电层与所述浮置栅极电分离，形成在所述第一控制栅极的侧壁和顶部上的第二介电层，形成在所述第一控制栅极的侧壁和顶部上的第二控制栅极为通过第二电介质层与第一控制栅极电分离，以及在衬底中形成的与第二控制栅极的两个边缘自对准的源极和漏极。

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