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41. 发明申请

US20090068823A1 Plasma Ion Doping Method and Apparatus 审中-公开
标题翻译：等离子体离子掺杂法和仪器
公开(公告)号：US20090068823A1
公开(公告)日：2009-03-12
申请号：US12145914
申请日：2008-06-25
申请人： Soo Jin Hong , Si-Young Choi , Tai-Su Park , Jin-Wook Lee , Jong-Hoon Kang , Mi-Jin Kim
发明人： Soo Jin Hong , Si-Young Choi , Tai-Su Park , Jin-Wook Lee , Jong-Hoon Kang , Mi-Jin Kim
IPC分类号： H01L21/02 , H01J37/08
CPC分类号： H01L21/2236 , H01J37/32412 , H01J37/32449
摘要： In plasma ion doping operations, a wafer is positioned on a susceptor within a reaction chamber and an ion doping source gas is plasmalyzed in an upper part of the reaction chamber above a major surface of the wafer while supplying a control gas into the reaction chamber in a lower part of the reaction chamber opposite the major surface of the wafer to thereby dope ions into the major surface of the wafer. The ion doping source gas may comprise at least one halide gas, and the control gas may comprise at least one depositing gas, such as a silane gas. In further embodiments, a diluent gas, such as an inert gas, may be supplied to the reaction chamber while supplying the ion doping source gas and the control gas. Related plasma ion doping apparatus are described.
摘要翻译：在等离子体离子掺杂操作中，将晶片定位在反应室内的基座上，并且将离子掺杂源气体在晶片的主表面上方的反应室上部进行等离子化，同时将控制气体供应到反应室中反应室的下部与晶片的主表面相对，从而将离子掺杂到晶片的主表面。离子掺杂源气体可以包括至少一种卤化物气体，并且控制气体可以包括至少一种沉积气体，例如硅烷气体。在另外的实施方案中，可以向反应室供应诸如惰性气体的稀释气体，同时供应离子掺杂源气体和控制气体。描述了相关的等离子体离子掺杂装置。

42. 发明申请

US20080296670A1 Semiconductor Devices Including Transistors Having a Recessed Channel Region and Methods of Fabricating the Same 审中-公开
标题翻译：包括具有嵌入式通道区域的晶体管的半导体器件及其制造方法
公开(公告)号：US20080296670A1
公开(公告)日：2008-12-04
申请号：US12128190
申请日：2008-05-28
申请人： Ja-Young Lee , Jin-Woo Lee , Sung-Hee Han , Tai-Su Park , Hyun-Sook Byun
发明人： Ja-Young Lee , Jin-Woo Lee , Sung-Hee Han , Tai-Su Park , Hyun-Sook Byun
IPC分类号： H01L49/00 , H01L21/26
CPC分类号： H01L29/66621 , H01L21/26586 , H01L29/78
摘要： Some embodiments of the present invention provide semiconductor devices including a gate trench in an active region of a semiconductor substrate and a gate electrode in the gate trench. A low-concentration impurity region is provided in the active region adjacent to a sidewall of the gate trench. A high-concentration impurity region is provided between the low-concentration impurity region and the sidewall of the gate trench and along the sidewall of the gate trench. Related methods of fabricating semiconductor devices are also provided herein.
摘要翻译：本发明的一些实施例提供半导体器件，其包括半导体衬底的有源区中的栅极沟槽和栅极沟槽中的栅电极。在与栅极沟槽的侧壁相邻的有源区域中提供低浓度杂质区域。在低浓度杂质区域和栅极沟槽的侧壁之间并且沿着栅极沟槽的侧壁设置高浓度杂质区域。本文还提供了制造半导体器件的相关方法。

43. 发明申请

US20080048262A1 Fin field effect transistor and method of forming the same 审中-公开
标题翻译： Fin场效应晶体管及其形成方法
公开(公告)号：US20080048262A1
公开(公告)日：2008-02-28
申请号：US11892320
申请日：2007-08-22
申请人： Deok-Hyung Lee , Sun-Ghil Lee , Gyeong-Ho Buh , Jong-Ryeol Yoo , Si-Young Choi , Tai-Su Park
发明人： Deok-Hyung Lee , Sun-Ghil Lee , Gyeong-Ho Buh , Jong-Ryeol Yoo , Si-Young Choi , Tai-Su Park
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/7851 , H01L29/41791 , H01L29/66636 , H01L29/66795 , H01L2029/7858
摘要： Provided are a fin field effect transistor (FinFET) with recess source/drain regions, and a method of forming the same. One example embodiment may provide a semiconductor device including a fin provided on a substrate and extending in a first direction, the fin including a stepped portion, and a gate electrode extending in a second direction crossing the first direction, and provided on a top surface and side surfaces of the stepped portion of the fin.
摘要翻译：提供具有凹陷源极/漏极区域的鳍式场效应晶体管（FinFET）及其形成方法。一个示例性实施例可以提供一种半导体器件，其包括设置在基板上并沿第一方向延伸的鳍，所述鳍包括台阶部分，以及沿与第一方向交叉的第二方向延伸的栅电极，并且设置在顶表面上翅片的台阶部分的侧表面。

44. 发明授权

US07015106B2 Double gate field effect transistor and method of manufacturing the same 失效
公开(公告)号：US07015106B2
公开(公告)日：2006-03-21
申请号：US10917026
申请日：2004-08-11
申请人： Jae-Man Yoon , Dong-gun Park , Gyo-young Jin , Yoshida Makoto , Tai-su Park
发明人： Jae-Man Yoon , Dong-gun Park , Gyo-young Jin , Yoshida Makoto , Tai-su Park
IPC分类号： H01L21/336 , H01L21/00 , H01L21/338
CPC分类号： H01L29/7851 , H01L21/823437 , H01L21/823481 , H01L21/84 , H01L27/1203 , H01L29/66795
摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

45. 发明授权

US06900090B2 Semiconductor device having a trench isolation structure and method for fabricating the same 有权
标题翻译：具有沟槽隔离结构的半导体器件及其制造方法
公开(公告)号：US06900090B2
公开(公告)日：2005-05-31
申请号：US10623918
申请日：2003-07-21
申请人： Tai-Su Park
发明人： Tai-Su Park
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238
CPC分类号： H01L21/76229
摘要： A device isolation structure in a semiconductor device and a method for fabricating the same are disclosed. A trench is formed in a semiconductor substrate to confine a plurality of active regions, an insulating material is deposited to fill the trench and the insulating material having a portion extending from the trench to above the semiconductor substrate, and a trench oxidation preventive film is formed on the insulating material. The semiconductor device preferably further includes a gate line extending in one direction on the semiconductor substrate having the trench oxidation-preventive film, and a sidewall spacer formed a sidewall of the gate line, wherein the trench oxidation-preventive film is disposed on the insulating material and disposed under the gate line and the sidewall spacer.
摘要翻译：公开了一种半导体器件中的器件隔离结构及其制造方法。在半导体衬底中形成沟槽以限制多个有源区，沉积绝缘材料以填充沟槽，并且绝缘材料具有从沟槽延伸到半导体衬底之上的部分，并且形成沟槽氧化防止膜在绝缘材料上。半导体器件优选还包括在具有沟槽防氧化膜的半导体衬底上的一个方向上延伸的栅极线和形成栅极线的侧壁的侧壁间隔，其中沟槽氧化防止膜设置在绝缘材料上并设置在栅极线和侧壁间隔物下。

46. 发明授权

US06537914B1 Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing 有权
标题翻译：集成电路器件隔离方法采用高选择性化学机械抛光
公开(公告)号：US06537914B1
公开(公告)日：2003-03-25
申请号：US09570225
申请日：2000-05-12
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee , Jung-yup Kim , Chang-ki Hong , Ho-kyu Kang
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee , Jung-yup Kim , Chang-ki Hong , Ho-kyu Kang
IPC分类号： H01L21302
CPC分类号： C09G1/02 , C09K3/1463 , H01L21/31053 , H01L21/76224
摘要： Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO2 group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO2 group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.
摘要翻译：用于集成电路的沟槽隔离方法可以通过使用高选择性化学机械抛光（CMP）操作来减少形成隔离层的不规则性。特别地，蚀刻衬底表面以形成沟槽。然后在衬底表面和沟槽中形成绝缘层。绝缘层使用包含CeO 2基团研磨剂的浆料进行化学机械抛光，以在沟槽中形成隔离层。包括CeO 2基研磨剂的浆料的CMP选择比可能足以使基板表面用作CMP停止。结果，可以在衬底表面上保持更一致的抛光水平，这可能导致隔离层中更均匀的厚度。

47. 发明授权

US06331469B1 Trench isolation structure, semiconductor device having the same, and trench isolation method 有权
标题翻译：沟槽隔离结构，具有相同的半导体器件，以及沟槽隔离方法
公开(公告)号：US06331469B1
公开(公告)日：2001-12-18
申请号：US09684822
申请日：2000-10-10
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.
摘要翻译：一种沟槽隔离结构，其通过对沟槽的顶部边缘进行舍入并增加在沟槽的顶部边缘处的氧化量，具有沟槽隔离结构的半导体器件和防止沟槽隔离结构的半导体器件，从而防止晶体管的隆起现象和反向窄宽度效应提供沟槽隔离方法。在这种沟槽隔离方法中，在半导体衬底的非有源区中形成沟槽。在沟槽的内壁上形成厚度为10至150埃的内壁氧化膜。在内壁氧化膜的表面上形成衬垫。沟槽填充有电介质膜。蚀刻衬垫的一部分，使得氮化硅衬垫的顶端从半导体衬底的表面凹陷。

48. 发明申请

US20140134812A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20140134812A1
公开(公告)日：2014-05-15
申请号：US14060806
申请日：2013-10-23
申请人： Dong-Chan KIM , Tai-Su PARK , Ju-Eun KIM , Ki-Hong NAM
发明人： Dong-Chan KIM , Tai-Su PARK , Ju-Eun KIM , Ki-Hong NAM
IPC分类号： H01L29/66 , H01L21/28 , H01L21/283 , H01L29/78 , H01L21/324
CPC分类号： H01L21/28185 , H01L21/02164 , H01L21/0228 , H01L21/28194 , H01L27/10814 , H01L27/10876 , H01L27/10888 , H01L29/513 , H01L29/517
摘要： A method of fabricating a semiconductor device includes forming a trench in a substrate, forming a pre-gate insulating film along side surfaces and a bottom surface of the trench, and oxidizing the pre-gate insulating film through a densification process.
摘要翻译：制造半导体器件的方法包括在衬底中形成沟槽，沿着沟槽的侧表面和底表面形成预栅绝缘膜，并通过致密化过程来氧化预栅绝缘膜。

49. 发明申请

US20120282769A1 METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING ELECTRICALLY CONDUCTIVE LAYERS THEREIN WITH PARTIALLY NITRIDATED SIDEWALLS 有权
标题翻译：形成具有部分硝化面的电导体层的集成电路装置的方法
公开(公告)号：US20120282769A1
公开(公告)日：2012-11-08
申请号：US13551251
申请日：2012-07-17
申请人： Jeong-Do Ryu , Si-Young CHOI , Yu-Gyun SHIN , Tai-Su PARK , Dong-Chan KIM , Jong-Ryeol YOO , Seong-Hoon JEONG , Jong-Hoon KANG
发明人： Jeong-Do Ryu , Si-Young CHOI , Yu-Gyun SHIN , Tai-Su PARK , Dong-Chan KIM , Jong-Ryeol YOO , Seong-Hoon JEONG , Jong-Hoon KANG
IPC分类号： H01L21/28
CPC分类号： H01L21/28061 , H01L21/28247 , H01L21/3211 , H01L21/32137 , H01L21/32139 , H01L27/10873 , H01L27/11 , H01L27/1104
摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
摘要翻译：形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

50. 发明申请

US20100072545A1 Recessed Channel Array Transistors, and Semiconductor Devices Including a Recessed Channel Array Transistor 有权
标题翻译：嵌入式通道阵列晶体管和包括嵌入式通道阵列晶体管的半导体器件
公开(公告)号：US20100072545A1
公开(公告)日：2010-03-25
申请号：US12563473
申请日：2009-09-21
申请人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L27/06 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/10894 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.
摘要翻译：凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。衬底可以具有有源区和隔离区。可以在活性区域中形成凹陷。栅极氧化物层可以形成在凹部和基板上。栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。第一部分可以包括大于第二部分厚度的约70％的厚度。栅极电极可以形成在栅极氧化物层上。源极/漏极区域可以形成在衬底中。因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

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