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41. 发明授权

US09041377B2 Pseudo constant on time control circuit and step-down regulator 有权
标题翻译：伪恒定的时间控制电路和降压调节器
公开(公告)号：US09041377B2
公开(公告)日：2015-05-26
申请号：US13538815
申请日：2012-06-29
申请人： Rui Wang , Zhengwei Zhang
发明人： Rui Wang , Zhengwei Zhang
IPC分类号： G05F1/00 , H02M3/158 , H02M1/00
CPC分类号： H02M3/158 , H02M2001/0003
摘要： A step-down regulator comprising a pseudo constant on time control circuit is disclosed, comprising an on-time generator configured to receive a switching signal provided by the step-down regulator and a control signal provided by the pseudo constant on time control circuit, and generates an on-time signal; a feedback control circuit configured to receive a feedback signal representative of the output voltage of the step-down regulator and generate an output signal; and a logic control circuit coupled to the on-time generator and the feedback control circuit to receive the on-time signal and the output signal and generating the control signal, and a power stage configured to receive an input voltage and the control signal and generate the switching signal.
摘要翻译：公开了一种包括伪恒定导通时间控制电路的降压调节器，包括接通时间发生器，其被配置为接收由降压调节器提供的开关信号和由伪恒定导通时间控制电路提供的控制信号，以及产生接通时间信号; 反馈控制电路，被配置为接收表示降压调节器的输出电压的反馈信号，并产生输出信号; 以及逻辑控制电路，其耦合到所述接通时间发生器和所述反馈控制电路，以接收所述接通时间信号和所述输出信号并产生所述控制信号;以及功率级，被配置为接收输入电压和所述控制信号并产生开关信号。

42. 发明授权

US08924898B2 System and method of designing instruction extensions to supplement an existing processor instruction set architecture 有权
标题翻译：设计指令扩展以补充现有处理器指令集架构的系统和方法
公开(公告)号：US08924898B2
公开(公告)日：2014-12-30
申请号：US12135502
申请日：2008-06-09
申请人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
发明人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F8/20 , G06F8/41 , G06F8/53 , G06F2217/04 , G06F2217/68
摘要： An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
摘要翻译：自动处理器设计工具使用标准化语言对定制的处理器指令集扩展进行描述，以开发目标指令集的可配置定义，实现指令集所需的电路的硬件描述语言描述，以及开发工具，如编译器，汇编器，调试器和模拟器，可用于开发处理器的应用程序并进行验证。处理器电路的实现可针对诸如面积，功耗，速度等的各种标准进行优化。一旦开发了处理器配置，就可以对其进行测试，并修改系统的输入以迭代地优化处理器实现。通过提供扩展和优化的限制域，该过程可以高度自动化，从而促进快速可靠的开发。

43. 发明授权

US08756192B2 Dispatching conflicting data changes 有权
标题翻译：调度冲突的数据更改
公开(公告)号：US08756192B2
公开(公告)日：2014-06-17
申请号：US12683440
申请日：2010-01-07
申请人： Rui Wang , Michael Habben , Qun Guo , Artem Oks
发明人： Rui Wang , Michael Habben , Qun Guo , Artem Oks
IPC分类号： G06F17/30
CPC分类号： G06F17/30575
摘要： A method for distributing one or more conflicting data changes. The method includes extracting data changes from the source site log, and applying the data changes to the destination site. The method then includes identifying one or more constraints for each data change and generating a hash value for each identified constraint. The method then dispatches the data changes into a plurality of streams based on the hash values. The hash values are used to identify conflicting data changes and determine how the data changes should be sent through the plurality of streams such that data changes are applied in parallel in the plurality of streams without violating any causal consistency constraints. The method then includes committing data changes in the plurality of streams to the destination site in a single transaction, creating a consistent transactional view.
摘要翻译：一种用于分发一个或多个冲突数据更改的方法。该方法包括从源站点日志中提取数据更改，并将数据更改应用于目标站点。该方法然后包括识别每个数据改变的一个或多个约束，并为每个识别的约束生成哈希值。然后，该方法基于散列值将数据变化分派到多个流中。哈希值用于识别冲突的数据变化并确定如何通过多个流发送数据变化，使得在多个流中并行地应用数据改变而不违反任何因果一致性约束。该方法然后包括在单个事务中将多个流中的数据更改提交到目标站点，从而创建一致的事务视图。

44. 发明授权

US08744994B2 Data filtering and optimization for ETL (extract, transform, load) processes 失效
标题翻译： ETL（提取，转换，加载）过程的数据过滤和优化
公开(公告)号：US08744994B2
公开(公告)日：2014-06-03
申请号：US12343021
申请日：2008-12-23
申请人： Ying Chen , Bin He , Rui Wang
发明人： Ying Chen , Bin He , Rui Wang
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30563 , G06F17/30592 , G06F17/30938
摘要： A method and system are disclosed for use with an ETL (Extract, Transform, Load) process, comprising optimizing a filter expression to select a subset of data and evaluating the filter expression on the data after the extracting, before the loading, but not during the transforming of the ETL process. The method and system optimizes the filtering using a pipelined evaluation for single predicate filtering and an adaptive optimization for multiple predicate filtering. The adaptive optimization includes an initial phase and a dynamic phase.
摘要翻译：公开了一种与ETL（提取，变换，加载）过程一起使用的方法和系统，包括优化滤波器表达式以选择数据子集，并且在加载之前对提取之后的数据评估滤波器表达式，但不在 ETL流程的转型。该方法和系统使用用于单个谓词过滤的流水线评估和针对多个谓词过滤的自适应优化来优化过滤。自适应优化包括初始阶段和动态阶段。

45. 发明授权

US08730364B2 Image sensor with pipelined column analog-to-digital converters 有权
标题翻译：具有流水线列模数转换器的图像传感器
公开(公告)号：US08730364B2
公开(公告)日：2014-05-20
申请号：US13080031
申请日：2011-04-05
申请人： Tiejun Dai , Rui Wang , Zhengyu Li , Joseph Yang , Min Qu , Yaowu Mo , Shaomin Ding , Guangbin Zhang
发明人： Tiejun Dai , Rui Wang , Zhengyu Li , Joseph Yang , Min Qu , Yaowu Mo , Shaomin Ding , Guangbin Zhang
IPC分类号： H04N5/335
CPC分类号： H04N5/378 , H04N5/3742
摘要： An image sensor includes a plurality of pixel cells organized into rows and columns of a pixel array. A bit line is coupled to each of the pixel cells within a line of the pixel array. Readout circuitry is coupled to the bit line to readout the image data from the pixel cells within the line. The readout circuitry includes a line amplifier coupled to the bit line to amplify the image data and first and second sample and convert circuits coupled in parallel to an output of the line amplifier to reciprocally and contemporaneously sample the image data and convert the image data from analog values to digital values.
摘要翻译：图像传感器包括被组织成像素阵列的行和列的多个像素单元。位线耦合到像素阵列的一行内的每个像素单元。读出电路耦合到位线以从线内的像素单元读出图像数据。读出电路包括耦合到位线以放大图像数据的线路放大器以及并行耦合到线路放大器的输出端的第一和第二采样和转换电路，以便对该图像数据进行往复同时采样并将图像数据从模拟值到数字值。

46. 发明授权

US08687387B2 Quasi-resonant controlled switching regulator and the method thereof 有权
标题翻译：准谐振控制开关调节器及其方法
公开(公告)号：US08687387B2
公开(公告)日：2014-04-01
申请号：US13218361
申请日：2011-08-25
申请人： Yike Li , Rui Wang , En Li
发明人： Yike Li , Rui Wang , En Li
IPC分类号： H02M3/335
CPC分类号： H02M3/156 , H02M2001/0058 , Y02B70/1425 , Y02B70/1491
摘要： A frequency limitation method used in a quasi-resonant controlled switching regulator is disclosed. The switching frequency is limited by setting a minimum time period, such as a minimum switching period or a minimum OFF time period. The minimum time period is varying according to the difference between the minimum time period of the previous cycle and an offset value, so as to eliminate the audible noise caused by the frequency hopping when the minimum OFF time period is close to the valley of a quasi-resonant signal.
摘要翻译：公开了一种在准谐振控制开关调节器中使用的频率限制方法。通过设置最小时间段（例如最小切换周期或最小关闭时间段）来限制开关频率。最小时间段根据前一周期的最小时间间隔和偏移值之间的差异而变化，以消除当最小关闭时间段接近准准的谷谷时跳频引起的可听见的噪声共振信号。

47. 发明申请

US20140066782A1 SYSTEM AND METHOD FOR DETERMINING A RESTING HEART RATE OF AN INDIVIDUAL 审中-公开
标题翻译：用于确定个体的静态心率的系统和方法
公开(公告)号：US20140066782A1
公开(公告)日：2014-03-06
申请号：US13598953
申请日：2012-08-30
申请人： Paul Stanley Addison , Rui Wang , James Nicholas Watson
发明人： Paul Stanley Addison , Rui Wang , James Nicholas Watson
IPC分类号： A61B5/024
CPC分类号： A61B5/024 , A61B5/02416 , A61B5/0245 , A61B5/0456 , A61B5/7239 , A61B7/00
摘要： A system to determine a resting heart rate (HR) of an individual. The system may include a monitor that is configured to be operatively connected to a sensor that obtains physiological signals from an individual. The monitor is configured to receive the physiological signals from the sensor. The monitor may include a validation module that is configured to analyze the physiological signals to identify valid heart beats from the physiological signals. The monitor may also include a rate-determining module that is configured to determine an HR signal that is based on the valid heart beats. The HR signal includes a series of data points. The monitor may also include an analysis module that is configured to analyze the HR signal and identify baseline data points from the series of data points. The analysis module is configured to calculate the resting HR based on the baseline data points.
摘要翻译：确定个体静息心率（HR）的系统。该系统可以包括被配置为可操作地连接到从个人获得生理信号的传感器的监视器。监视器被配置为从传感器接收生理信号。监视器可以包括验证模块，其被配置为分析生理信号以从生理信号识别有效心跳。监视器还可以包括速率确定模块，其被配置为基于有效的心脏跳动来确定HR信号。 HR信号包括一系列数据点。监视器还可以包括分析模块，其被配置为分析HR信号并从所述一系列数据点识别基准数据点。分析模块被配置为基于基线数据点计算静息HR。

48. 发明授权

US08612390B2 Lightweight caching of transaction log for sequential access 有权
标题翻译：轻量级缓存事务日志以进行顺序访问
公开(公告)号：US08612390B2
公开(公告)日：2013-12-17
申请号：US13098647
申请日：2011-05-02
申请人： Rui Wang , Peter Byrne
发明人： Rui Wang , Peter Byrne
IPC分类号： G06F17/00 , G06F7/00
CPC分类号： G06F17/3048 , G06F17/30457
摘要： Searching cached log blocks. A method includes performing a first search on cached log blocks for a log block having a first log block ID. The log blocks are cached and organized into sequentially ordered log buffers in memory. Adjacent sequentially ordered log buffers are double linked to each other. Each log buffer includes a complete range of log blocks from a starting log block ID to an ending log block ID. As part of the first search one or more links are followed, forward and/or backward, to one or more other log buffers. The method may further include determining that the first log block is not found by following one or more links forward and/or backward to one or more other log buffers and as a result, follow one or more covering pointers to one or more log buffers to search for the first log block.
摘要翻译：搜索缓存的日志块。一种方法包括对具有第一个日志块ID的日志块执行对高速缓存的日志块的第一次搜索。日志块被缓存并组织成内存中的顺序排序的日志缓冲区。相邻的顺序排序的日志缓冲区相互双重链接。每个日志缓冲区包括从起始日志块ID到结束日志块ID的完整范围的日志块。作为第一次搜索的一部分，一个或多个链接被跟随，向前和/或向后到一个或多个其他日志缓冲器。该方法还可以包括通过将一个或多个链路向前和/或向后追溯到一个或多个其它日志缓冲区来确定不发现第一日志块，并且因此，遵循一个或多个覆盖指针到一个或多个日志缓冲器搜索第一个日志块。

49. 发明授权

US08521196B2 Method and system for implementing multimedia broadcast/multicast service 有权
标题翻译：实现多媒体广播/组播业务的方法和系统
公开(公告)号：US08521196B2
公开(公告)日：2013-08-27
申请号：US11764329
申请日：2007-06-18
申请人： Rui Wang
发明人： Rui Wang
IPC分类号： H04W4/00
CPC分类号： H04L12/189 , H04W36/00 , H04W72/005
摘要： A method and a system for implementing MBMS. According to embodiments of the present invention, the MBMS are born on different multimedia broadcast multicast bearers; each multimedia broadcast multicast bearers corresponds to a multimedia broadcast multicast area; an association relationship between the different multimedia broadcast multicast bearers of MBMS of a same type is set at a network side; when the UE switches between different multimedia broadcast multicast areas, the network side provides the UE with the multimedia broadcast multicast bearer of the multimedia broadcast multicast area where the UE is located currently according to the association relationship between the multimedia broadcast multicast bearers corresponding to the MBMS request by the UE. The method and the system in accordance with the present invention can support MBMS better.
摘要翻译：一种用于实现MBMS的方法和系统。根据本发明的实施例，MBMS出生在不同的多媒体广播多播承载上; 每个多媒体广播组播承载对应一个多媒体广播组播区; 在网络侧设置相同种类的MBMS的不同多媒体广播组播承载之间的关联关系; 当UE在不同的多媒体广播多播区域之间切换时，网络侧根据MBMS所对应的多媒体广播组播承载之间的关联关系向UE提供UE所在的多媒体广播组播区域的多媒体广播组播承载由UE请求。根据本发明的方法和系统可以更好地支持MBMS。

50. 发明授权

US08514024B2 High power-supply rejection ratio amplifying circuit 有权
标题翻译：高电源抑制比放大电路
公开(公告)号：US08514024B2
公开(公告)日：2013-08-20
申请号：US13218370
申请日：2011-08-25
申请人： Rui Wang , Jinyan Lin , Huijie Zhao , Yunping Lang
发明人： Rui Wang , Jinyan Lin , Huijie Zhao , Yunping Lang
IPC分类号： H03F3/04
CPC分类号： H03F1/30
摘要： The embodiments of the present invention disclose a high power-supply rejection ratio (PSRR) amplifier circuit. The amplifier circuit comprises a low dropout regulator, a negative charge pump and an amplifier. The output voltages of the negative charge pump and the low dropout regulators don't track the change of input voltage. Therefore the amplifier circuit has high PSRR.
摘要翻译：本发明的实施例公开了一种高电源抑制比（PSRR）放大器电路。该放大器电路包括一个低压差稳压器，一个负电荷泵和一个放大器。负电荷泵和低压差稳压器的输出电压不跟踪输入电压的变化。因此放大器电路具有高PSRR。

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