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1. 发明申请

US20120113306A1 IMAGE SENSOR WITH PIPELINED COLUMN ANALOG-TO-DIGITAL CONVERTERS 有权
标题翻译：图像传感器与管道柱模数转换器
公开(公告)号：US20120113306A1
公开(公告)日：2012-05-10
申请号：US13080031
申请日：2011-04-05
申请人： Tiejun Dai , Rui Wang , Zhengyu Li , Joseph Yang , Min Qu , Yaowu Mo , Shaomin Ding , Guangbin Zhang
发明人： Tiejun Dai , Rui Wang , Zhengyu Li , Joseph Yang , Min Qu , Yaowu Mo , Shaomin Ding , Guangbin Zhang
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N5/378 , H04N5/3742
摘要： An image sensor includes a plurality of pixel cells organized into rows and columns of a pixel array. A bit line is coupled to each of the pixel cells within a line of the pixel array. Readout circuitry is coupled to the bit line to readout the image data from the pixel cells within the line. The readout circuitry includes a line amplifier coupled to the bit line to amplify the image data and first and second sample and convert circuits coupled in parallel to an output of the line amplifier to reciprocally and contemporaneously sample the image data and convert the image data from analog values to digital values.
摘要翻译：图像传感器包括被组织成像素阵列的行和列的多个像素单元。位线耦合到像素阵列的一行内的每个像素单元。读出电路耦合到位线以从线内的像素单元读出图像数据。读出电路包括耦合到位线以放大图像数据的线路放大器以及并行耦合到线路放大器的输出端的第一和第二采样和转换电路，以便对该图像数据进行往复同时采样并将图像数据从模拟值到数字值。

2. 发明授权

US08730364B2 Image sensor with pipelined column analog-to-digital converters 有权
标题翻译：具有流水线列模数转换器的图像传感器
公开(公告)号：US08730364B2
公开(公告)日：2014-05-20
申请号：US13080031
申请日：2011-04-05
申请人： Tiejun Dai , Rui Wang , Zhengyu Li , Joseph Yang , Min Qu , Yaowu Mo , Shaomin Ding , Guangbin Zhang
发明人： Tiejun Dai , Rui Wang , Zhengyu Li , Joseph Yang , Min Qu , Yaowu Mo , Shaomin Ding , Guangbin Zhang
IPC分类号： H04N5/335
CPC分类号： H04N5/378 , H04N5/3742
摘要： An image sensor includes a plurality of pixel cells organized into rows and columns of a pixel array. A bit line is coupled to each of the pixel cells within a line of the pixel array. Readout circuitry is coupled to the bit line to readout the image data from the pixel cells within the line. The readout circuitry includes a line amplifier coupled to the bit line to amplify the image data and first and second sample and convert circuits coupled in parallel to an output of the line amplifier to reciprocally and contemporaneously sample the image data and convert the image data from analog values to digital values.
摘要翻译：图像传感器包括被组织成像素阵列的行和列的多个像素单元。位线耦合到像素阵列的一行内的每个像素单元。读出电路耦合到位线以从线内的像素单元读出图像数据。读出电路包括耦合到位线以放大图像数据的线路放大器以及并行耦合到线路放大器的输出端的第一和第二采样和转换电路，以便对该图像数据进行往复同时采样并将图像数据从模拟值到数字值。

3. 发明申请

US20130089175A1 ARITHMETIC COUNTER CIRCUIT, CONFIGURATION AND APPLICATION FOR HIGH PERFORMANCE CMOS IMAGE SENSORS 有权
标题翻译：算术计数器电路，高性能CMOS图像传感器的配置和应用
公开(公告)号：US20130089175A1
公开(公告)日：2013-04-11
申请号：US13365790
申请日：2012-02-03
申请人： Yaowu Mo , Chen Xu , Min Qu , Tiejun Dai , Rui Wang , Xiaodong Luo
发明人： Yaowu Mo , Chen Xu , Min Qu , Tiejun Dai , Rui Wang , Xiaodong Luo
IPC分类号： H03K29/00
CPC分类号： H04N5/347 , H04N5/3532 , H04N5/355 , H04N5/3745 , H04N5/378
摘要： An arithmetic counter circuit for high performance CMOS image sensors includes a plurality of flip-flops of a plurality of counter stages and a plurality of multiplexers of the plurality of counter stages being coupled to the plurality of flip-flops. Each of the plurality of multiplexers coupled to receive control signals including at least one of a toggle signal, a keep signal, a shift enable signal, or a mode signal. The control signals select the output of each of the plurality of multiplexers. Each of the plurality of flip-flops is coupled to be in one of a toggle state, a keep state, a reset state or a set state based on inputs received from the plurality of multiplexers. Other embodiments are described.
摘要翻译：用于高性能CMOS图像传感器的算术计数器电路包括多个计数器级的多个触发器，并且多个计数器级的多个多路复用器耦合到多个触发器。多个多路复用器中的每一个被耦合以接收包括切换信号，保持信号，移位使能信号或模式信号中的至少一个的控制信号。控制信号选择多个多路复用器中的每一个的输出。多个触发器中的每一个基于从多个多路复用器接收的输入被耦合成处于切换状态，保持状态，复位状态或设置状态之一。描述其他实施例。

4. 发明授权

US08576979B2 Arithmetic counter circuit, configuration and application for high performance CMOS image sensors 有权
标题翻译：算术计数器电路，高性能CMOS图像传感器的配置和应用
公开(公告)号：US08576979B2
公开(公告)日：2013-11-05
申请号：US13365790
申请日：2012-02-03
申请人： Yaowu Mo , Chen Xu , Min Qu , Tiejun Dai , Rui Wang , Xiaodong Luo
发明人： Yaowu Mo , Chen Xu , Min Qu , Tiejun Dai , Rui Wang , Xiaodong Luo
IPC分类号： H03K23/64 , H03K21/02 , H03K21/00 , H03K23/00
CPC分类号： H04N5/347 , H04N5/3532 , H04N5/355 , H04N5/3745 , H04N5/378
摘要： An arithmetic counter circuit for high performance CMOS image sensors includes a plurality of flip-flops of a plurality of counter stages and a plurality of multiplexers of the plurality of counter stages being coupled to the plurality of flip-flops. Each of the plurality of multiplexers coupled to receive control signals including at least one of a toggle signal, a keep signal, a shift enable signal, or a mode signal. The control signals select the output of each of the plurality of multiplexers. Each of the plurality of flip-flops is coupled to be in one of a toggle state, a keep state, a reset state or a set state based on inputs received from the plurality of multiplexers. Other embodiments are described.
摘要翻译：用于高性能CMOS图像传感器的算术计数器电路包括多个计数器级的多个触发器，并且多个计数器级的多个多路复用器耦合到多个触发器。多个多路复用器中的每一个被耦合以接收包括切换信号，保持信号，移位使能信号或模式信号中的至少一个的控制信号。控制信号选择多个多路复用器中的每一个的输出。多个触发器中的每一个基于从多个多路复用器接收的输入被耦合成处于切换状态，保持状态，复位状态或设置状态之一。描述其他实施例。

5. 发明授权

US08933385B2 Hybrid analog-to-digital converter having multiple ADC modes 有权
标题翻译：具有多种ADC模式的混合模数转换器
公开(公告)号：US08933385B2
公开(公告)日：2015-01-13
申请号：US13543470
申请日：2012-07-06
申请人： Rui Wang , Liping Deng , Tiejun Dai
发明人： Rui Wang , Liping Deng , Tiejun Dai
IPC分类号： G01J1/44 , H03M1/12 , H03M1/38
CPC分类号： H03M1/145 , H03M1/466 , H03M1/56
摘要： A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.
摘要翻译：公开了一种具有用于产生数字信号位的逐次逼近寄存器（SAR）ADC模式和用于产生数字信号的附加位的斜坡ADC模式的混合ADC。当处于SAR ADC模式时，控制电路被配置为禁止斜坡信号发生器; 禁用计数器并且使能寄存器来控制偏移级以设置提供给ADC的比较器的输入的偏移电压的幅度。当处于斜坡ADC模式时，控制电路被配置为使得斜坡信号发生器能够向比较器的输入端提供斜坡信号; 使计数器响应于比较器的输出开始提供数字计数; 并禁用寄存器，使偏移级不提供偏移电压。

6. 发明申请

US20140008515A1 HYBRID ANALOG-TO-DIGITAL CONVERTER HAVING MULTIPLE ADC MODES 有权
标题翻译：具有多种ADC模式的混合模数转换器
公开(公告)号：US20140008515A1
公开(公告)日：2014-01-09
申请号：US13543470
申请日：2012-07-06
申请人： Rui Wang , Liping Deng , Tiejun Dai
发明人： Rui Wang , Liping Deng , Tiejun Dai
IPC分类号： H03M1/38 , H03M1/14 , H01L27/146
CPC分类号： H03M1/145 , H03M1/466 , H03M1/56
摘要： A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.
摘要翻译：公开了一种具有用于产生数字信号位的逐次逼近寄存器（SAR）ADC模式和用于产生数字信号的附加位的斜坡ADC模式的混合ADC。当处于SAR ADC模式时，控制电路被配置为禁止斜坡信号发生器; 禁用计数器并且使能寄存器来控制偏移级以设置提供给ADC的比较器的输入的偏移电压的幅度。当处于斜坡ADC模式时，控制电路被配置为使得斜坡信号发生器能够向比较器的输入端提供斜坡信号; 使计数器响应于比较器的输出开始提供数字计数; 并禁用寄存器，使偏移级不提供偏移电压。

7. 发明公开

US20240098376A1 COLUMN ARITHMETIC LOGIC UNIT DESIGN FOR DUAL CONVERSION GAIN SENSOR SUPPORTING CORRELATED MULTIPLE SAMPLING AND THREE READOUT PHASE DETECTION AUTOFOCUS 审中-公开
公开(公告)号：US20240098376A1
公开(公告)日：2024-03-21
申请号：US17934196
申请日：2022-09-21
申请人： Lihang Fan , Nijun Jiang , Rui Wang
发明人： Lihang Fan , Nijun Jiang , Rui Wang
IPC分类号： H04N5/243 , H04N5/378
CPC分类号： H04N5/243 , H04N5/378
摘要： An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage. The feedback stage includes first conversion gain feedback latches configured to latch outputs of the pre-latch stage having a first conversion gain and second conversion gain feedback latches configured to latch outputs of the pre-latch stage having a second conversion gain.

8. 外观设计

USD948360S1 Gas detector 有权
公开(公告)号：USD948360S1
公开(公告)日：2022-04-12
申请号：US29767390
申请日：2021-01-22
申请人： Rui Wang
设计人： Rui Wang

9. 外观设计

USD897350S1 Protective case for mobile device 有权
公开(公告)号：USD897350S1
公开(公告)日：2020-09-29
申请号：US29735407
申请日：2020-05-20
申请人： Rui Wang
设计人： Rui Wang
摘要： FIG. 1 is a front and top perspective view of a protective case for mobile device, showing my design.
FIG. 2 is a front elevation view thereof.
FIG. 3 is a rear elevation view thereof.
FIG. 4 is a right side elevation view thereof.
FIG. 5 is a left side elevation view thereof.
FIG. 6 is a top plan view thereof; and,
FIG. 7 is a bottom plan view thereof.
The broken lines are for environmental structure, boundaries, or illustrative purposes only and form no part of the claimed designs to be patented.

10. 发明授权

US10733573B2 Method, apparatus, and system for pushing information 有权
公开(公告)号：US10733573B2
公开(公告)日：2020-08-04
申请号：US15551187
申请日：2016-02-04
申请人： Alibaba Group Holding Limited , Yu Wang , Rui Wang , Jinming Wang , Jiqiu Xu , Weiwei Fu , Wanli Min
发明人： Yu Wang , Rui Wang , Jinming Wang , Jiqiu Xu , Weiwei Fu , Wanli Min
IPC分类号： G06Q10/10 , G06Q40/00 , G06Q10/06
摘要： The disclosed embodiments describe a method, apparatus, and system for pushing information. In one embodiment, the method comprises: receiving dynamic spatio-temporal behavior data of a moving individual; conducting an analysis according to historical dynamic spatio-temporal behavior data of the moving individual to acquire spatio-temporal behavioral characteristics of the moving individual; determining appropriate information as matching information for the moving individual according to the spatio-temporal behavioral characteristics of the moving individual in combination with dynamic spatio-temporal behavior data of the moving individual at a current time; and sending the matching information to the moving individual. In the method of the disclosure, behavioral characteristics of a moving individual are analyzed to obtain habit and preference characteristics of the moving individual. Targeted push information is sent, thereby solving the problem of pushed information having less diversified, targeted, and not so accurate content.

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