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41. 发明授权

US08738924B2 Electronic system and digital right management methods thereof 有权
标题翻译：电子系统及其数字权利管理方法
公开(公告)号：US08738924B2
公开(公告)日：2014-05-27
申请号：US12107206
申请日：2008-04-22
申请人： Zhun Huang , Jiin Lai
发明人： Zhun Huang , Jiin Lai
IPC分类号： H04L9/32
CPC分类号： G06F21/10 , G06F21/445 , G06F2221/2129
摘要： An electronic system is provided, in which a smart chip, a smart chip controller, a processor, a system memory, and an access management module is provided. The smart chip controller communicates with the smart chip. The processor performs a mutual authentication with the smart chip. The system memory is accessible to the smart chip and the processor. The access management module is coupled between the processor and the smart chip controller. The access management module prevents the processor accessing a certain range of the system memory according to a block command from the smart chip controller, in response of that the mutual authentication between the processor and the smart chip is failed.
摘要翻译：提供了一种电子系统，其中提供智能芯片，智能芯片控制器，处理器，系统存储器和访问管理模块。智能芯片控制器与智能芯片通信。处理器与智能芯片执行相互认证。智能芯片和处理器可以访问系统内存。访问管理模块耦合在处理器和智能芯片控制器之间。响应于处理器和智能芯片之间的相互认证失败，访问管理模块防止处理器根据来自智能芯片控制器的块命令访问系统存储器的特定范围。

42. 发明授权

US08521938B2 Universal serial bus host controller and control method thereof 有权
标题翻译：通用串行总线主机控制器及其控制方法
公开(公告)号：US08521938B2
公开(公告)日：2013-08-27
申请号：US12900309
申请日：2010-10-07
申请人： Zhiqiang Hui , Jiin Lai , Shanna Pang , Di Dai
发明人： Zhiqiang Hui , Jiin Lai , Shanna Pang , Di Dai
IPC分类号： G06F13/36
CPC分类号： G06F13/385 , G06F2213/3812
摘要： A USB host controller is provided. The USB host controller is capable of communicating with multiple USB apparatuses having endpoints and sends a request to a first endpoint. The USB host controller includes a first storage and a first control unit. The first control unit stores endpoint information from the first endpoint into the first storage when the first endpoint issues an unready transaction packet in response to the request. The unready transaction packet indicates that the first endpoint is not ready.
摘要翻译：提供USB主机控制器。 USB主机控制器能够与具有端点的多个USB设备通信，并向第一端点发送请求。 USB主机控制器包括第一存储器和第一控制单元。当第一端点响应于该请求发出未获得的事务分组时，第一控制单元将端点信息从第一端点存储到第一存储器中。未完成的事务数据包指示第一个端点尚未就绪。

43. 发明授权

US08270840B2 Backward compatible optical USB device 有权
标题翻译：向后兼容的光学USB设备
公开(公告)号：US08270840B2
公开(公告)日：2012-09-18
申请号：US12818361
申请日：2010-06-18
申请人： Jiin Lai
发明人： Jiin Lai
IPC分类号： H04B10/02 , H04B10/04
CPC分类号： G06F13/426 , G06F13/385
摘要： An optical USB device includes an electro-optical converter configured to receive optical signals from an optical fiber and to convert them into first electrical signals and configured to receive second electrical signals and to convert them into optical signals for transmission to the optical fiber. A USB 3.0 pin-compatible connector is coupled to the electro-optical converter. The pin-compatible connector is configured for coupling to a USB 3.0 connector of another USB device. The pin-compatible connector includes a first pair of pins configured for transmitting the first electrical signals from the optical USB device. The pin-compatible connector also includes a second pair of pins configured for receiving the second electrical signals into the optical USB device. The pin-compatible connector also includes a third pair of pins configured for transceiving third electrical signals according to a non-USB serial bus interface protocol to control and configure the electro-optical converter.
摘要翻译：光学USB装置包括电光转换器，其被配置为从光纤接收光信号并将其转换为第一电信号并且被配置为接收第二电信号并将其转换成用于传输到光纤的光信号。 USB 3.0引脚兼容的连接器耦合到电光转换器。引脚兼容连接器被配置为耦合到另一个USB设备的USB 3.0连接器。引脚兼容连接器包括被配置为从光学USB设备传输第一电信号的第一对引脚。引脚兼容连接器还包括被配置为将第二电信号接收到光学USB设备中的第二对引脚。引脚兼容连接器还包括第三对引脚，其被配置用于根据非USB串行总线接口协议收发第三电信号，以控制和配置电光转换器。

44. 发明授权

US08234416B2 Apparatus interoperable with backward compatible optical USB device 有权
标题翻译：设备可与后向兼容的光学USB设备互操作
公开(公告)号：US08234416B2
公开(公告)日：2012-07-31
申请号：US12818342
申请日：2010-06-18
申请人： Jiin Lai
发明人： Jiin Lai
IPC分类号： G06F3/00 , G06F15/00
CPC分类号： G06F13/4081 , G06F2213/0042
摘要： An apparatus configured to couple to a universal serial bus (USB) 3.0 connector. The apparatus includes a management controller configured to couple to the USB 3.0 connector. The management controller is configured to detect from behavior on the D+ and D− pins of the USB 3.0 connector whether a device plugged into the USB 3.0 connector is a conventional USB 3.0 device or an optical USB device, where the optical USB device employs one of the D+ and D− pins of the USB 3.0 connector to transmit a data signal and the other to transmit a clock signal.
摘要翻译：一种被配置为耦合到通用串行总线（USB）3.0连接器的装置。该装置包括配置成耦合到USB 3.0连接器的管理控制器。管理控制器被配置为根据USB 3.0连接器的D +和D-引脚的行为来检测插入USB 3.0连接器的设备是否是传统的USB 3.0设备或光学USB设备，其中光学USB设备采用 USB 3.0连接器的D +和D-引脚传输数据信号，另一个发送时钟信号。

45. 发明申请

US20110255873A1 Optical Transceiver Modules and Systems and Optical Transceiving Methods 有权
标题翻译：光收发模块和系统以及光收发方法
公开(公告)号：US20110255873A1
公开(公告)日：2011-10-20
申请号：US12950122
申请日：2010-11-19
申请人： Jinkuan Tang , Jiin Lai
发明人： Jinkuan Tang , Jiin Lai
IPC分类号： H04B10/02
CPC分类号： H04B10/40
摘要： An optical transceiver module includes a receiving unit, a transmission driving unit, and a terminal control unit. The receiving unit outputs a receiver lost signal. The transmission driving unit includes a positive receiving signal terminal and a negative receiving signal terminal. The terminal control unit is coupled between the positive receiving signal terminal and the negative receiving signal terminal. The terminal control unit controls whether a differential terminator impedance is coupled between the positive receiving signal terminal and the negative receiving signal terminal according to the receiver lost signal.
摘要翻译：光收发模块包括接收单元，传输驱动单元和终端控制单元。接收单元输出接收机丢失信号。发送驱动单元包括正接收信号端子和负接收信号端子。终端控制单元耦合在正接收信号端子和负接收信号端子之间。终端控制单元根据接收机丢失信号来控制差分终端阻抗是否连接在正接收信号端子和负接收信号端子之间。

46. 发明申请

US20110243568A1 BACKWARD COMPATIBLE OPTICAL USB DEVICE 有权
标题翻译：背面兼容的OPTICAL USB DEVICE
公开(公告)号：US20110243568A1
公开(公告)日：2011-10-06
申请号：US12818361
申请日：2010-06-18
申请人： Jiin Lai
发明人： Jiin Lai
IPC分类号： H04B10/28
CPC分类号： G06F13/426 , G06F13/385
摘要： An optical USB device includes an electro-optical converter configured to receive optical signals from an optical fiber and to convert them into first electrical signals and configured to receive second electrical signals and to convert them into optical signals for transmission to the optical fiber. A USB 3.0 pin-compatible connector is coupled to the electro-optical converter. The pin-compatible connector is configured for coupling to a USB 3.0 connector of another USB device. The pin-compatible connector includes a first pair of pins configured for transmitting the first electrical signals from the optical USB device. The pin-compatible connector also includes a second pair of pins configured for receiving the second electrical signals into the optical USB device. The pin-compatible connector also includes a third pair of pins configured for transceiving third electrical signals according to a non-USB serial bus interface protocol to control and configure the electro-optical converter.
摘要翻译：光学USB装置包括电光转换器，其被配置为从光纤接收光信号并将其转换为第一电信号并且被配置为接收第二电信号并将其转换成用于传输到光纤的光信号。 USB 3.0引脚兼容的连接器耦合到电光转换器。引脚兼容连接器被配置为耦合到另一个USB设备的USB 3.0连接器。引脚兼容连接器包括被配置为从光学USB设备传输第一电信号的第一对引脚。引脚兼容连接器还包括被配置为将第二电信号接收到光学USB设备中的第二对引脚。引脚兼容连接器还包括第三对引脚，其被配置用于根据非USB串行总线接口协议收发第三电信号，以控制和配置电光转换器。

47. 发明申请

US20110066795A1 STREAM CONTEXT CACHE SYSTEM 有权
标题翻译： STREAM语音高速缓存系统
公开(公告)号：US20110066795A1
公开(公告)日：2011-03-17
申请号：US12829345
申请日：2010-07-01
申请人： XIU-LI GUO , JIIN LAI , ZHI-QIANG HUI , SHUANG-SHUANG QIN
发明人： XIU-LI GUO , JIIN LAI , ZHI-QIANG HUI , SHUANG-SHUANG QIN
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0862 , G06F12/0875 , G06F12/10 , G06F2212/6028
摘要： The present invention is directed to a stream context cache system, which primarily includes a cache and a mapping table. The cache stores plural stream contexts, and the mapping table stores associated stream context addresses in a system memory. Consequently, a host may, according to the content of the mapping table, directly retrieve the stream context that is pre-fetched and stored in the cache, rather than read the stream context from the system memory.
摘要翻译：本发明涉及一种流上下文高速缓存系统，其主要包括高速缓存和映射表。高速缓存存储多个流上下文，并且映射表将相关联的流上下文地址存储在系统存储器中。因此，主机可以根据映射表的内容直接检索预取和存储在高速缓存中的流上下文，而不是从系统存储器读取流上下文。

48. 发明授权

US07610497B2 Power management system with a bridge logic having analyzers for monitoring data quantity to modify operating clock and voltage of the processor and main memory 有权
标题翻译：电源管理系统具有桥逻辑，具有用于监视数据量的分析仪，以修改处理器和主存储器的工作时钟和电压
公开(公告)号：US07610497B2
公开(公告)日：2009-10-27
申请号：US11048191
申请日：2005-02-01
申请人： Ruei-Ling Lin , Jiin Lai , Hung-Yi Kuo
发明人： Ruei-Ling Lin , Jiin Lai , Hung-Yi Kuo
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A core logic coupled to a main memory of a computer, comprising an analyzer and a power management unit. The analyzer monitors access request traffic load of main memory. The power management unit employs various power performance trade-off activities with the knowledge of the monitored traffic load according to the state machine.
摘要翻译：耦合到计算机的主存储器的核心逻辑，包括分析器和电源管理单元。分析仪监控主存储器的访问请求流量负载。电力管理单元根据状态机采用各种电力性能权衡活动，了解监控的业务负载。

49. 发明授权

US07594058B2 Chipset supporting a peripheral component interconnection express (PCI-E) architecture 有权
标题翻译：芯片组支持外围组件互连快速（PCI-E）架构
公开(公告)号：US07594058B2
公开(公告)日：2009-09-22
申请号：US11267498
申请日：2005-11-07
申请人： Peter Chia , Chad Tsai , Jiin Lai , Edward Su , Chih-Kuo Kao
发明人： Peter Chia , Chad Tsai , Jiin Lai , Edward Su , Chih-Kuo Kao
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled to said first port-arbiter. The first URD logic includes an onboard range table and a PCI-E device range table for detecting the data of onboard access or peer-to-peer access. The microprocessor receives and processes the data from the first URD logic for said onboard access. The DARD logic receives the data from the microprocessor. The DARD logic decodes a device range of a downstream request of the data. The device arbiter is coupled to the DARD logic and the first URD logic for dispatching the data to one of the first PCI-E port.
摘要翻译：使用PCI-E架构的本计算系统包括至少一个第一PCI-E端口，第一端口仲裁器，第一URD逻辑，微处理器，DARD逻辑和设备仲裁器。第一个端口仲裁器从第一个PCI-E端口接收数据。第一URD逻辑耦合到所述第一端口仲裁器。第一个URD逻辑包括板载范围表和PCI-E设备范围表，用于检测板上访问或对等访问的数据。微处理器接收并处理来自用于所述板载存取的第一URD逻辑的数据。 DARD逻辑从微处理器接收数据。 DARD逻辑解码数据的下游请求的设备范围。设备仲裁器耦合到DARD逻辑和第一个URD逻辑，用于将数据分配到第一个PCI-E端口之一。

50. 发明申请

US20080313471A1 ELECTRONIC SYSTEM AND DIGITAL RIGHT MANAGEMENT METHODS THEREOF 有权
标题翻译：电子系统及其数字权限管理方法
公开(公告)号：US20080313471A1
公开(公告)日：2008-12-18
申请号：US12107206
申请日：2008-04-22
申请人： Zhun Huang , Jiin Lai
发明人： Zhun Huang , Jiin Lai
IPC分类号： H04K1/00
CPC分类号： G06F21/10 , G06F21/445 , G06F2221/2129
摘要： An electronic system is provided, in which a smart chip, a smart chip controller, a processor, a system memory, and an access management module is provided. The smart chip controller communicates with the smart chip. The processor performs a mutual authentication with the smart chip. The system memory is accessible to the smart chip and the processor. The access management module is coupled between the processor and the smart chip controller. The access management module prevents the processor accessing a certain range of the system memory according to a block command from the smart chip controller, in response of that the mutual authentication between the processor and the smart chip is failed.
摘要翻译：提供了一种电子系统，其中提供智能芯片，智能芯片控制器，处理器，系统存储器和访问管理模块。智能芯片控制器与智能芯片通信。处理器与智能芯片执行相互认证。智能芯片和处理器可以访问系统内存。访问管理模块耦合在处理器和智能芯片控制器之间。响应于处理器和智能芯片之间的相互认证失败，访问管理模块防止处理器根据来自智能芯片控制器的块命令访问系统存储器的特定范围。

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