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41. 发明申请

US20100261346A1 CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT 失效
标题翻译：具有条带划分的参考平面电路的电路制造和设计技术
公开(公告)号：US20100261346A1
公开(公告)日：2010-10-14
申请号：US12823316
申请日：2010-06-25
申请人： Sungjun Chun , Anand Haridass , Roger D. Weekly
发明人： Sungjun Chun , Anand Haridass , Roger D. Weekly
IPC分类号： H01L21/768 , G06F17/50
CPC分类号： G06F17/5077 , H05K1/0219 , H05K1/0237 , H05K1/0253 , H05K3/4602 , H05K3/4652 , H05K2201/09536 , H05K2201/09672 , H05K2201/0969 , H05K2201/09718 , Y10T29/49117 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , Y10T428/24322
摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.
摘要翻译：具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起信号承载PTH的顶部（或底部）到传输线参考平面。为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括在通过空隙减少与信号承载PTH的耦合并且维持信号路径导体。

42. 发明申请

US20100259289A1 Detecting Open Ground Connections in Surface Mount Connectors 失效
标题翻译：检测表面贴装连接器中的开放接地连接
公开(公告)号：US20100259289A1
公开(公告)日：2010-10-14
申请号：US12420089
申请日：2009-04-08
申请人： Anand Haridass , Jesus Montanez , Xiaomin Shen , Sungjun Chun
发明人： Anand Haridass , Jesus Montanez , Xiaomin Shen , Sungjun Chun
IPC分类号： G01R31/02 , H01L25/00
CPC分类号： G01R31/026 , G01R31/043 , G01R31/2812 , H05K3/341
摘要： A device may include a current source for connecting to a printed circuit board. The device may also include a first FET switch pack and a second FET switch pack for connecting to the surface mount connector of the printed circuit board. Additionally, the device may include a FET controller connected to the first FET switch pack and the second FET switch pack. The FET controller may be utilized for connecting a first FET and a second FET to the first region of the surface mount connector. The FET controller may be configured for supplying the current to the first region of the surface mount connector to produce at least one continuous heat signature characteristic of an improperly connected ground pin. A thermal monitoring module may be used to identify the improper physical connection.
摘要翻译：设备可以包括用于连接到印刷电路板的电流源。该装置还可以包括用于连接到印刷电路板的表面安装连接器的第一FET开关组件和第二FET开关组件。另外，该装置可以包括连接到第一FET开关组和第二FET开关组的FET控制器。 FET控制器可以用于将第一FET和第二FET连接到表面安装连接器的第一区域。 FET控制器可以被配置为将电流提供给表面安装连接器的第一区域，以产生不正确连接的接地引脚的至少一个连续的热标记特性。热监测模块可用于识别不正确的物理连接。

43. 发明授权

US07721119B2 System and method to optimize multi-core microprocessor performance using voltage offsets 失效
标题翻译：使用电压补偿优化多核微处理器性能的系统和方法
公开(公告)号：US07721119B2
公开(公告)日：2010-05-18
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译：提出了使用电压偏移来优化多核微处理器性能的系统和方法。多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。

44. 发明授权

US07614141B2 Fabricating substrates having low inductance via arrangements 失效
标题翻译：通过布置制造具有低电感的基板
公开(公告)号：US07614141B2
公开(公告)日：2009-11-10
申请号：US11355713
申请日：2006-02-16
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Roger D. Weekly
IPC分类号： H01K3/10
CPC分类号： H05K1/162 , H01L23/49827 , H01L23/50 , H01L23/642 , H01L2924/0002 , H05K1/0306 , H05K3/4611 , H05K3/4629 , H05K2201/09609 , H05K2201/09627 , Y10T29/49117 , Y10T29/49155 , H01L2924/00
摘要： A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.
摘要翻译：提供了一种用于多层陶瓷（MLC）衬底的低电感通孔布置。通过MLC衬底和示例性实施例的通孔布置，给定接触焊盘阵列的通孔电感减小。这种减少是通过引入T-jogs和附加通孔来实现的。这些T形点动和附加通孔形成额外的电流路径，从而产生额外的并联电感，从而减小通路电感。在一个说明性实施例中，附加的T形点动和通孔被添加到接触焊盘阵列的中心部分。 T-jogs由MLC的布线层中的两个点动组成，每个点动都朝向与接触垫阵列中的相邻接触焊盘相关联的通孔。这些额外的T形点动和通孔形成与现有循环平行的额外的电流回路，从而减小通孔的总电感。

45. 发明授权

US07503111B2 Method for increasing wiring channels/density under dense via fields 失效
标题翻译：增加密集通道的布线通道/密度的方法
公开(公告)号：US07503111B2
公开(公告)日：2009-03-17
申请号：US11095741
申请日：2005-03-31
申请人： Anand Haridass , Dierk Kaller , Erich Klink , Gisbert Gerhard Thomke
发明人： Anand Haridass , Dierk Kaller , Erich Klink , Gisbert Gerhard Thomke
IPC分类号： H05K3/02
CPC分类号： G06F17/5077 , H01L21/486 , H01L23/49822 , H01L23/49838 , H01L2924/0002 , H05K1/111 , H05K1/112 , H05K3/0005 , H05K3/429 , H05K2201/09227 , H05K2201/10734 , Y10T29/49156 , H01L2924/00
摘要： A method for increasing the wiring channels/density under dense via fields of a circuit board are provided. With the method, the power/ground lines for the circuit board are designed to be provided in an orthogonal or diagonal pattern. The land grid array (LGA)/ball grid array (BGA) makes contact only on the surface pads of the printed circuit board with no plated through holes/vias underneath these surface pads. This opens up wiring channels, which previously used to be occupied by plated through holes and anti-pads, that can now be used for maximizing signal line wiring routing.
摘要翻译：提供了一种用于增加电路板密集通孔的布线通道/密度的方法。利用该方法，电路板的电源/接地线被设计成以正交或对角线图案提供。栅格阵列（LGA）/球栅阵列（BGA）仅在印刷电路板的表面焊盘上接触，在这些表面焊盘下方没有电镀通孔/通孔。这打开了以前用于通过电镀通孔和防焊盘占用的接线通道，现在可以用于最大化信号线路由布线。

46. 发明申请

US20090031270A1 Design Method and System for Minimizing Blind Via Current Loops 有权
标题翻译：设计方法和系统，最大限度地减少盲电流环路
公开(公告)号：US20090031270A1
公开(公告)日：2009-01-29
申请号：US11829179
申请日：2007-07-27
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Roger D. Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , H05K1/0216 , H05K1/115 , H05K3/0005 , H05K2201/09636
摘要： A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.
摘要翻译：用于最小化盲通过电流回路的设计方法和系统提供了电互连结构设计的改进，而不需要广泛的电磁分析。检查通过携带关键信号的盲目附近的其他通孔是否适合于进行对应于由两个金属平面之间的层到另一层之间的过渡而被破坏的关键信号的返回电流。检查通过（s）的返回电流的距离，并且如果距离大于指定的阈值，则设计被调整以减小距离。如果盲目通过转换到外部层，合适的通孔将盲通孔内部的参考平面连接到外部端子。如果过渡在内层之间，合适的通孔是连接围绕由盲孔通过的参考平面的两个参考平面的通孔。

47. 发明申请

US20080294414A1 SYSTEM DC ANALYSIS METHODOLOGY 有权
标题翻译：系统直流分析方法
公开(公告)号：US20080294414A1
公开(公告)日：2008-11-27
申请号：US12187164
申请日：2008-08-06
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao Gia-Harvey Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao Gia-Harvey Truong , Roger D. Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer program product is provided for power delivery analysis and design for a hierarchical system. The product includes a storage medium, readable by a processing circuit, for storing instructions for execution by the processing circuit for facilitating a method. The method includes building a model corresponding to each element of the hierarchical system, and compiling a repository that contains models corresponding to each element, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method also includes performing optimized gridding for each element, the net list, the domain list, the component list, the pin list, and the layer list; assembling a system model from the models contained in the repository; flattening the system model by converting the system model to a flattened system model that consists entirely of resistors; and running a simulation on the flattened system model.
摘要翻译：提供计算机程序产品用于分层系统的功率传递分析和设计。该产品包括可由处理电路读取的存储介质，用于存储由处理电路执行以便于方法的指令。该方法包括构建与分级系统的每个元素相对应的模型，以及编译包含与每个元素对应的模型的仓库，其中仓库包括网络列表，域列表，组件列表，引脚列表和层列表。该方法还包括对每个元素，网络列表，域列表，组件列表，引脚列表和层列表执行优化的网格化; 从存储库中包含的模型组装系统模型; 通过将系统模型转换为完全由电阻组成的扁平化系统模型来平坦化系统模型; 并在扁平化系统模型上运行模拟。

48. 发明申请

US20080127192A1 Method and System for Using Multiple-Core Integrated Circuits 审中-公开
标题翻译：使用多核集成电路的方法和系统
公开(公告)号：US20080127192A1
公开(公告)日：2008-05-29
申请号：US11466903
申请日：2006-08-24
申请人： Louis B. Capps , Thomas J. Dewkett , Joanne Ferris , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
发明人： Louis B. Capps , Thomas J. Dewkett , Joanne Ferris , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
IPC分类号： G06F9/46
CPC分类号： G06F9/5044 , G06F1/3203 , G06F1/329 , Y02D10/24
摘要： A method, apparatus, and computer program product for using a multi-core integrated circuit having cores with differing performance characteristics. The cores are arranged into high and low performance groups and tasks are assigned according to their priority to either a high or low performance group.
摘要翻译：一种用于使用具有不同性能特征的核的多核集成电路的方法，装置和计算机程序产品。核心被排列成高性能组和低性能组，任务根据其优先级分配给高性能组或低性能组。

49. 发明申请

US20070283172A1 Mitigate Power Supply Noise Response by Throttling Execution Units Based Upon Voltage Sensing 失效
标题翻译：通过基于电压检测的截止执行单元来缓解电源噪声响应
公开(公告)号：US20070283172A1
公开(公告)日：2007-12-06
申请号：US11420820
申请日：2006-05-30
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.
摘要翻译：提供了一种通过基于电路中的电压感测的节流执行单元来减轻电源和配电系统噪声响应的系统。感测单元感测电路的电压。感测单元确定另一个执行单元的执行是否会导致电路电压降至阈值以下。响应于确定另一执行单元的执行将导致电路电压降低到阈值水平以下，执行单元被调节。

50. 发明申请

US20070260444A1 System DC Analysis Methodology 有权
标题翻译：系统直流分析方法
公开(公告)号：US20070260444A1
公开(公告)日：2007-11-08
申请号：US11380058
申请日：2006-04-25
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm O'Reilly , Bao Gia-Harvey Truong , Roger Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm O'Reilly , Bao Gia-Harvey Truong , Roger Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of power delivery analysis and design for a hierarchical system including building a model corresponding to each element of the hierarchical system, compiling a repository that contains the models corresponding to each element of the hierarchical system, assembling a system model from the models contained in the repository, flattening the system model, and running a simulation on the flattened system model.
摘要翻译：一种用于分层系统的功率传递分析和设计的方法，包括构建与分层系统的每个元件相对应的模型，编译包含与分层系统的每个元件相对应的模型的存储库，从包含的模型组装系统模型存储库，平整系统模型，并在平面化系统模型上运行仿真。

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