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1. 发明授权

US07460986B2 System DC Analysis Methodology 有权
标题翻译：系统直流分析方法
公开(公告)号：US07460986B2
公开(公告)日：2008-12-02
申请号：US11380058
申请日：2006-04-25
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao Gia-Harvey Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao Gia-Harvey Truong , Roger D. Weekly
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5036
摘要： A method is provided for power delivery analysis and design for a hierarchical system. The method includes building a model corresponding to each element of the hierarchical system, compiling a repository that contains the models corresponding to each element of the hierarchical system, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method further includes performing optimized gridding for each element of the hierarchial system, the net list, the domain list, the component list, the pin list, and the layer list and assembling a system model from the models contained in the repository. Also, the method includes flattening the system model by converting the system model to a flattened system model that consists entirely of resistors, and running a simulation on the flattened system model.
摘要翻译：提供了一种用于分层系统的功率传递分析和设计的方法。该方法包括建立与分级系统的每个元素相对应的模型，编译包含对应于分层系统的每个元素的模型的存储库，其中存储库包括网络列表，域列表，组件列表，引脚列表，和一个图层列表。该方法还包括对分层系统的每个元素，网络列表，域列表，组件列表，引脚列表和层列表执行优化的网格化，以及从存储库中包含的模型组装系统模型。此外，该方法包括通过将系统模型转换为完全由电阻组成的扁平化系统模型，并在扁平化系统模型上运行模拟来平坦化系统模型。

2. 发明授权

US08055486B2 Power delivery analysis and design 有权
标题翻译：电力分配和设计
公开(公告)号：US08055486B2
公开(公告)日：2011-11-08
申请号：US12187164
申请日：2008-08-06
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao Gia-Harvey Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao Gia-Harvey Truong , Roger D. Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer program product is provided for power delivery analysis and design for a hierarchical system. The product includes a storage medium, readable by a processing circuit, for storing instructions for execution by the processing circuit for facilitating a method. The method includes building a model corresponding to each element of the hierarchical system, and compiling a repository that contains models corresponding to each element, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method also includes performing optimized gridding for each element, the net list, the domain list, the component list, the pin list, and the layer list; assembling a system model from the models contained in the repository; flattening the system model by converting the system model to a flattened system model that consists entirely of resistors; and running a simulation on the flattened system model.
摘要翻译：提供计算机程序产品用于分层系统的功率传递分析和设计。该产品包括可由处理电路读取的存储介质，用于存储由处理电路执行以便于方法的指令。该方法包括构建与分级系统的每个元素相对应的模型，以及编译包含与每个元素对应的模型的仓库，其中仓库包括网络列表，域列表，组件列表，引脚列表和层列表。该方法还包括对每个元素，网络列表，域列表，组件列表，引脚列表和层列表执行优化的网格化; 从存储库中包含的模型组装系统模型; 通过将系统模型转换为完全由电阻组成的扁平化系统模型来平坦化系统模型; 并在扁平化系统模型上运行模拟。

3. 发明申请

US20080294414A1 SYSTEM DC ANALYSIS METHODOLOGY 有权
标题翻译：系统直流分析方法
公开(公告)号：US20080294414A1
公开(公告)日：2008-11-27
申请号：US12187164
申请日：2008-08-06
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao Gia-Harvey Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao Gia-Harvey Truong , Roger D. Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer program product is provided for power delivery analysis and design for a hierarchical system. The product includes a storage medium, readable by a processing circuit, for storing instructions for execution by the processing circuit for facilitating a method. The method includes building a model corresponding to each element of the hierarchical system, and compiling a repository that contains models corresponding to each element, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method also includes performing optimized gridding for each element, the net list, the domain list, the component list, the pin list, and the layer list; assembling a system model from the models contained in the repository; flattening the system model by converting the system model to a flattened system model that consists entirely of resistors; and running a simulation on the flattened system model.
摘要翻译：提供计算机程序产品用于分层系统的功率传递分析和设计。该产品包括可由处理电路读取的存储介质，用于存储由处理电路执行以便于方法的指令。该方法包括构建与分级系统的每个元素相对应的模型，以及编译包含与每个元素对应的模型的仓库，其中仓库包括网络列表，域列表，组件列表，引脚列表和层列表。该方法还包括对每个元素，网络列表，域列表，组件列表，引脚列表和层列表执行优化的网格化; 从存储库中包含的模型组装系统模型; 通过将系统模型转换为完全由电阻组成的扁平化系统模型来平坦化系统模型; 并在扁平化系统模型上运行模拟。

4. 发明申请

US20070260444A1 System DC Analysis Methodology 有权
标题翻译：系统直流分析方法
公开(公告)号：US20070260444A1
公开(公告)日：2007-11-08
申请号：US11380058
申请日：2006-04-25
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm O'Reilly , Bao Gia-Harvey Truong , Roger Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm O'Reilly , Bao Gia-Harvey Truong , Roger Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of power delivery analysis and design for a hierarchical system including building a model corresponding to each element of the hierarchical system, compiling a repository that contains the models corresponding to each element of the hierarchical system, assembling a system model from the models contained in the repository, flattening the system model, and running a simulation on the flattened system model.
摘要翻译：一种用于分层系统的功率传递分析和设计的方法，包括构建与分层系统的每个元件相对应的模型，编译包含与分层系统的每个元件相对应的模型的存储库，从包含的模型组装系统模型存储库，平整系统模型，并在平面化系统模型上运行仿真。

5. 发明授权

US06772250B2 Boundary scannable one bit precompensated CMOS driver with compensating pulse width control 失效
标题翻译：边界可扫描一位预补偿CMOS驱动器，具有补偿脉宽控制
公开(公告)号：US06772250B2
公开(公告)日：2004-08-03
申请号：US09810058
申请日：2001-03-15
申请人： Daniel Mark Dreps , Anand Haridass , Bao Gia-Harvey Truong
发明人： Daniel Mark Dreps , Anand Haridass , Bao Gia-Harvey Truong
IPC分类号： G06F1300
CPC分类号： G06F13/4077 , H03K19/00346 , H03K19/017581
摘要： An improved data driver, method, and system for driving data with an improved slew rate and eye opening is provided. In one embodiment, the data driver includes a non-precompensating data driver and a precompensating data driver. The non-precompensating driver generates a non-precompensating output data pulse corresponding to input data. The non-precompensating data driver generates a pulse in response to every input data bit received. The precompensating driver generates the precompensating pulse only in response to a transition from one data state to a second data state between consecutive data bits. The precompensating data pulse is shorter in duration than the non-precompensating output data. The output data from the data drive is the sum of the non-precompensating output data pulse and the precompensating output data pulse.
摘要翻译：提供了一种改进的数据驱动程序，方法和系统，用于驱动具有改进的压摆率和眼睛开度的数据。在一个实施例中，数据驱动器包括非预补偿数据驱动器和预补偿数据驱动器。非预补偿驱动器产生对应于输入数据的非预补偿输出数据脉冲。非预补偿数据驱动器响应于接收的每个输入数据位产生脉冲。预补偿驱动器仅响应于在连续数据位之间从一个数据状态到第二数据状态的转变而产生预补偿脉冲。预补偿数据脉冲的持续时间比非预补偿输出数据短。来自数据驱动器的输出数据是非预补偿输出数据脉冲和预补偿输出数据脉冲之和。

6. 发明授权

US06930507B2 Thevenins receiver 失效
标题翻译：戴维宁接收器
公开(公告)号：US06930507B2
公开(公告)日：2005-08-16
申请号：US10616845
申请日：2003-07-10
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Bao Gia-Harvey Truong
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Bao Gia-Harvey Truong
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H04L25/0296
摘要： A termination network has multiple resistors forming multiple voltage dividers with a common node. Half of the resistors are coupled to the positive power supply voltage with P channel field effect transistors (PFETs) and the other half are coupled to the negative or ground power supply voltage with N channel FETs (NFETs). Logic signals are used to control the gates of the FETs. By modifying which FETs are ON, the termination network can be selectively controlled to produce various offset levels with the same impedance level. The impedance levels may also be modified while maintaining the same offset level. A delay circuit may be selectively employed to feedback control signals after a selected delay time to adjust the threshold level to dynamically or statically optimize signal reception.
摘要翻译：终端网络具有多个电阻器，其形成具有公共节点的多个分压器。一半的电阻器与P沟道场效应晶体管（PFET）耦合到正电源电压，另一半电阻与N沟道FET（NFET）耦合到负极或接地电源电压。逻辑信号用于控制FET的栅极。通过修改哪些FET为ON，可以选择性地控制终端网络以产生具有相同阻抗水平的各种偏移电平。阻抗水平也可以被修改，同时保持相同的偏移水平。可以选择性地采用延迟电路来在所选择的延迟时间之后反馈控制信号以调整阈值电平以动态地或静态地优化信号接收。

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