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31. 发明授权

US06668301B2 Microcontroller with flexible interface to external device 有权
标题翻译：微控制器具有与外部设备的灵活接口
公开(公告)号：US06668301B2
公开(公告)日：2003-12-23
申请号：US09774911
申请日：2001-01-30
申请人： Tommaso Bacigalupo
发明人： Tommaso Bacigalupo
IPC分类号： G06F1314
CPC分类号： G06F13/385
摘要： A semiconductor device is disclosed that has a plurality of I/O pins that are configurable to selectively output three sets of signals selected from the group consisting of (i) a read enable signal and a write enable signal, (ii) a combined read and write enable signal, (iii) a read enable signal and a pair of byte write enable signals, and (iv) a row address strobe signal, and a column address strobe signal.
摘要翻译：公开了一种半导体器件，其具有多个I / O引脚，其可配置为选择性地输出从由（i）读使能信号和写使能信号组成的组中选择的三组信号，（ii）组合读和写使能信号，（iii）读使能信号和一对字节写使能信号，以及（iv）行地址选通信号和列地址选通信号。

32. 发明授权

US06665760B1 Group shifting and level shifting rotational arbiter system 有权
标题翻译：组移和水平移动旋转仲裁系统
公开(公告)号：US06665760B1
公开(公告)日：2003-12-16
申请号：US09677035
申请日：2000-09-29
申请人： Gary Dan Dotson
发明人： Gary Dan Dotson
IPC分类号： G06F1314
CPC分类号： G06F13/364 , G06F13/30
摘要： An arbiter system comprises a plurality of hardware resources, a common resource, and an arbiter. The plurality of hardware resources are divided into groups of hardware resources and are coupled to the common resource and the arbiter. The arbiter controls which of the plurality of hardware resources has priority to access to the common resource. The arbiter includes a group shifting arbiter which shifts priority among the groups of hardware resources and a level shifting arbiter which separately shifts priority among the hardware resources within each of the groups. An error checking value generator system comprises a general purpose DMA controller and an arithmetic circuit. The arithmetic circuit is coupled to receive data from the general purpose DMA controller. The arithmetic circuit generates an error checking value based on the data received from the general purpose DMA controller and based on a polynomial equation. The arithmetic circuit is capable of being programmed with a plurality of different polynomial equations usable to generate error checking values of different types.
摘要翻译：仲裁系统包括多个硬件资源，公共资源和仲裁器。多个硬件资源被划分成一组硬件资源，并且被耦合到公共资源和仲裁器。仲裁器控制多个硬件资源中的哪一个具有访问公共资源的优先权。仲裁器包括一组移动仲裁器，该组移位仲裁器在硬件资源组之间转移优先权，以及一个电平移动仲裁器，其分别转移每个组内的硬件资源之间的优先级。误差检测值发生器系统包括通用DMA控制器和运算电路。算术电路被耦合以从通用DMA控制器接收数据。算术电路基于从通用DMA控制器接收的数据并基于多项式方程来生成错误校验值。算术电路能够用可用于生成不同类型的错误检查值的多个不同的多项式方程进行编程。

33. 发明授权

US06665748B1 Specialized PCMCIA host adapter for use with low cost microprocessors 失效
标题翻译：专门用于低成本微处理器的PCMCIA主机适配器
公开(公告)号：US06665748B1
公开(公告)日：2003-12-16
申请号：US09752495
申请日：2000-12-28
申请人： John T. Slater , Scott Wilkinson , James Slater
发明人： John T. Slater , Scott Wilkinson , James Slater
IPC分类号： G06F1314
CPC分类号： G06F13/28
摘要： Apparatus and method for providing DMA transfers between an adapter card with or with out DMA capabilities and a system CPU with DMA capabilities. An adapter DMA controller circuit resides between the system CPU and the adapter card. This adapter DMA controller allows the system to run in immediate mode which allows the system CPU to talk to the adapter card as if the adapter DMA controller was not there. The system can also run in DMA mode. In this mode the system CPU sets up the system DMA controller and the adapter DMA controller. The adapter DMA controller takes over sending or receiving data to the adapter card and then requesting a DMA transfer with the system DMA controller. The transfer of data between the adapter DMA controller and the adapter does not use any system CPU resources such as the data and address busses. The system CPU is free to use the system resources to continue operation.
摘要翻译：在具有或具有DMA能力的适配器卡和具有DMA功能的系统CPU之间提供DMA传输的装置和方法。适配器DMA控制器电路驻留在系统CPU和适配器卡之间。此适配器DMA控制器允许系统以即时模式运行，这允许系统CPU与适配器卡通信，就好像适配器DMA控制器不在那里。系统也可以在DMA模式下运行。在此模式下，系统CPU设置系统DMA控制器和适配器DMA控制器。适配器DMA控制器接收发送或接收数据到适配器卡，然后请求与系统DMA控制器进行DMA传输。适配器DMA控制器和适配器之间的数据传输不会使用任何系统CPU资源，如数据和地址总线。系统CPU可以自由使用系统资源来继续运行。

34. 发明授权

US06662246B2 Two-dimensional memory access in image processing systems 有权
标题翻译：图像处理系统中的二维存储器访问
公开(公告)号：US06662246B2
公开(公告)日：2003-12-09
申请号：US10218184
申请日：2002-08-12
申请人： Hooman Honary , Anatoly Moskalev
发明人： Hooman Honary , Anatoly Moskalev
IPC分类号： G06F1314
CPC分类号： G06T1/60
摘要： A two-dimensional direct memory access system that maximizes processing resources in image processing systems. The present invention includes a two-dimensional direct memory access machine. Also, it employs a ping-pong style memory buffer to assist in the transfer and management of data. In certain applications of the invention, the type of data used by the invention is image data. The two-dimensional direct memory access machine transfers a specific cross sectional area of the image data to a processor. The efficient method of providing the processor only with the specific cross sectional area of the image data that is to be processed at a given time provides decreased processing time and a better utilization of processing resources within the two-dimensional direct memory access system. The present invention may be contained in a variety of image processing systems operating as either a peripheral or a stand alone device including but not limited to color photo-copy machines, color facsimiles, color printers, black and white printers, digital cameras, and digital printers. In certain embodiments, the two-dimensional direct memory access system exchanges image data between random access memory and a digital signal processor using the two-dimensional direct memory access machine and the ping-pong style memory buffer.
摘要翻译：二维直接存储器访问系统，使图像处理系统中的处理资源最大化。本发明包括二维直接存储器存取机。此外，它采用乒乓风格的内存缓冲区来协助数据的传输和管理。在本发明的某些应用中，本发明使用的数据类型是图像数据。二维直接存储器访问机将图像数据的特定横截面区域传送到处理器。为处理器提供仅在给定时间处理的图像数据的特定横截面面积的有效方法提供了减少的处理时间和更好地利用二维直接存储器存取系统内的处理资源。本发明可以包含在作为外围设备或独立设备操作的各种图像处理系统中，该设备包括但不限于彩色复印机，彩色传真机，彩色打印机，黑白打印机，数码相机和数字打印机在某些实施例中，二维直接存储器访问系统使用二维直接存储器访问机和乒乓式存储器缓冲器在随机存取存储器和数字信号处理器之间交换图像数据。

35. 发明授权

US06662245B1 Apparatus and system for blocking memory access during DMA transfer 失效
标题翻译：用于在DMA传输期间阻止存储器访问的装置和系统
公开(公告)号：US06662245B1
公开(公告)日：2003-12-09
申请号：US09912993
申请日：2001-07-25
申请人： Yair Aizenberg , Laurent Alloin , Peter Kleewein , Yong Je Lim
发明人： Yair Aizenberg , Laurent Alloin , Peter Kleewein , Yong Je Lim
IPC分类号： G06F1314
CPC分类号： G06F13/28
摘要： The present invention is directed to an apparatus and system for selectively inhibiting access to a memory during a DMA block transfer. In accordance with one embodiment of the present invention, the system includes memory, a DMA engine, and logic configured so that when a control signal is asserted, the logic blocks the DMA engine's request for access to memory and generates an acknowledgment of the request, such that the DMA engine performs a DMA transfer without accessing data in memory.
摘要翻译：本发明涉及一种用于在DMA块传输期间选择性地禁止对存储器的访问的装置和系统。根据本发明的一个实施例，该系统包括存储器，DMA引擎和配置为使得当控制信号被断言时的逻辑，该逻辑阻止DMA引擎访问存储器的请求，并产生对该请求的确认，使得DMA引擎执行DMA传输而不访问存储器中的数据。

36. 发明授权

US06662244B1 Information terminal 失效
标题翻译：信息终端
公开(公告)号：US06662244B1
公开(公告)日：2003-12-09
申请号：US09629726
申请日：2000-07-31
申请人： Masahiro Takahashi
发明人： Masahiro Takahashi
IPC分类号： G06F1314
CPC分类号： H04M1/0214 , H04M1/0245 , H04M2250/16
摘要： An information terminal made up of a first housing 2 having a display section 5 and a second housing 3 having an input/display section 11 and can be made very small when said first housing 2 and said second housing 3 are folded relative to each other. An enhanced degree of operability in terms of inputting characters and displaying a large volume of data is provided.
摘要翻译：信息终端由具有显示部分5的第一壳体2和具有输入/显示部分11的第二壳体3组成，并且当所述第一壳体2和第二壳体3相对于彼此折叠时，可以使其非常小。提供了在输入字符和显示大量数据方面提高了可操作性的程度。

37. 发明授权

US06654829B2 SCSI connector 失效
公开(公告)号：US06654829B2
公开(公告)日：2003-11-25
申请号：US10260932
申请日：2002-09-30
申请人： Michael S. Zandy , George J. Scholhamer , William C. Galloway
发明人： Michael S. Zandy , George J. Scholhamer , William C. Galloway
IPC分类号： G06F1314
CPC分类号： H05K7/1459
摘要： In a computer system having redundant SCSI controllers cards, a SCSI controller interface for receiving multiple interchangeable SCSI controller cards is configured so that the data bus paths between each of the SCSI controller slots and the controller circuitry do not cross.

38. 发明授权

US06651115B2 DMA controller and coherency-tracking unit for efficient data transfers between coherent and non-coherent memory spaces 有权
标题翻译： DMA控制器和一致性跟踪单元，用于在相干和非相干存储空间之间进行有效的数据传输
公开(公告)号：US06651115B2
公开(公告)日：2003-11-18
申请号：US10336720
申请日：2003-01-06
申请人： Andrew V. Anderson
发明人： Andrew V. Anderson
IPC分类号： G06F1314
CPC分类号： G06F13/1668
摘要： In a computer system, an agent, a DMA controller and a memory controller are provided, each in communication with a bus. The DMA controller and the memory controller also can communicate with each other via a second communication path. The computer system may include a memory provided in communication with the memory controller having a coherent memory space and a non-coherent memory space. The DMA controller transfers a portion of data from the coherent memory space with a portion of data from the non-coherent memory space with a single transaction on the external bus.
摘要翻译：在计算机系统中，提供代理，DMA控制器和存储器控制器，每个与总线通信。 DMA控制器和存储器控制器也可以经由第二通信路径相互通信。计算机系统可以包括与具有相干存储器空间和非相干存储器空间的存储器控制器通信提供的存储器。 DMA控制器使用来自非相干存储器空间的一部分数据从相干存储器空间与外部总线上的单个事务传输一部分数据。

39. 发明授权

US06643717B1 Flow control 有权
标题翻译：流量控制
公开(公告)号：US06643717B1
公开(公告)日：2003-11-04
申请号：US09437413
申请日：1999-11-10
申请人： Mark D. Rustad , Scott A. Davidson , Jeffrey T. Rabe , Robert J. Lipe , Steven R. Wahl
发明人： Mark D. Rustad , Scott A. Davidson , Jeffrey T. Rabe , Robert J. Lipe , Steven R. Wahl
IPC分类号： G06F1314
CPC分类号： G06F13/4286
摘要： A method for controlling a transmitter for a serial data port is provided. The method includes receiving a set of data at the serial data port. The data in the set of data is compared with a selected pattern of bits. When data in the set of data matches the selected pattern of bits, a bit in a register is set. When the bit in the register is set, transmissions stop. The method further includes processing the set of data to determine a flow control state. When processing the set of data determines that the flow control state is a first state, transmissions re-start.
摘要翻译：提供了一种用于控制串行数据端口的发送器的方法。该方法包括在串行数据端口处接收一组数据。数据组中的数据与选定的位模式进行比较。当数据组中的数据与所选择的模式匹配时，寄存器中的位被置位。当寄存器中的位置1时，传输停止。该方法还包括处理该组数据以确定流量控制状态。当处理该组数据时，确定流量控制状态是第一状态，传输重新启动。

40. 发明授权

US06636925B1 Bus interface circuit preparation apparatus and recording medium 有权
标题翻译：总线接口电路准备设备和记录介质
公开(公告)号：US06636925B1
公开(公告)日：2003-10-21
申请号：US09686928
申请日：2000-10-11
申请人： Motohide Otsubo , Kazutoshi Wakabayashi , Yuichi Maruyama
发明人： Motohide Otsubo , Kazutoshi Wakabayashi , Yuichi Maruyama
IPC分类号： G06F1314
CPC分类号： G06F12/0646
摘要： An apparatus for automatically preparing a bus interface preparation apparatus is provided which is capable of preventing duplication of addresses of registers and memories. When data of a hardware description 10 are input into the extracting portion 101, the extracting portion 101 extracts from the data whether the memory element is a memory device or an FF. The extracting portion 101 reads the top address and the address size of the memory element when the memory is the memory element and reads address when the memory is an FF, and the thus read data are output to the address competition detecting portion 103. The address competition detecting portion 103 detects competition of the addresses by determining whether the address information stored in the bit data memory portion 102 includes 1. The output portion 104 converts the data concerning address of the memory into a description language of the hardware of the bus interface circuit.
摘要翻译：提供一种用于自动准备总线接口准备装置的装置，其能够防止寄存器和存储器的地址的重复。当将硬件描述10的数据输入到提取部分101中时，提取部分101从数据中提取存储器元件是存储器还是FF。当存储器是存储器元件时，提取部分101读取存储器元件的顶部地址和地址大小，并且当存储器是FF时读取地址，并且将这样读取的数据输出到地址竞争检测部分103.地址竞争检测部分103通过确定存储在比特数据存储部分102中的地址信息是否包括1来检测地址的竞争。输出部分104将关于存储器的地址的数据转换为总线接口电路的硬件的描述语言。

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