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1. 发明授权

US06629117B2 Method for computing a fast fourier transform and associated circuit for addressing a data memory 有权
公开(公告)号：US06629117B2
公开(公告)日：2003-09-30
申请号：US10126602
申请日：2002-06-05
申请人： Yair Aizenberg , Yue-Peng Zheng
发明人： Yair Aizenberg , Yue-Peng Zheng
IPC分类号： G06F1714
CPC分类号： G06F17/142
摘要： The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way. More particularly, after computing a first set of complex butterfly operations (each having the same twiddle value) in a given computation stage, a first complex butterfly operation (having a different twiddle value) of a second set of complex butterfly operations, is computed in that stage. Thereafter, all remaining complex butterfly operations (having the same value) in that stage will be computed. This methodology will be repeated until all butterfly operations are calculated in each stage. An addressing circuit is also provided for addressing a data memory in a system for computing a FFT, the system having a data memory for storing data values and a coefficient memory for storing coefficient values.

2. 发明授权

US06615227B2 Circuit and method for computing a fast fourier transform 有权
标题翻译：用于计算快速傅里叶变换的电路和方法
公开(公告)号：US06615227B2
公开(公告)日：2003-09-02
申请号：US10247144
申请日：2002-09-19
申请人： Yair Aizenberg , Daniel Amrany , Yue-Peng Zheng
发明人： Yair Aizenberg , Daniel Amrany , Yue-Peng Zheng
IPC分类号： G06F1714
CPC分类号： G06F17/142
摘要： A processing circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2's compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a data pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.
摘要翻译：公开了一种用于计算快速傅里叶变换（FFT）的处理电路。在一个实施例中，处理电路包括一个存储器件，一个乘法器，一个检测器，一个状态机以及一个用于执行2的系数的补偿的电路。存储器存储设备存储数据值和系数（或旋转）值。检测器将数据指针与状态机集成。检测器设计用于识别对称线（通过存储器地址）。状态机当被检测器通知已经遇到对称线时，适当地调整系数，虚拟符号或输入到乘法器的真实符号。

3. 发明授权

US06477554B1 Circuit and method for computing a fast fourier transform 有权
标题翻译：用于计算快速傅里叶变换的电路和方法
公开(公告)号：US06477554B1
公开(公告)日：2002-11-05
申请号：US09398636
申请日：1999-09-17
申请人： Yair Aizenberg , Daniel Amrany , Yue-Peng Zheng
发明人： Yair Aizenberg , Daniel Amrany , Yue-Peng Zheng
IPC分类号： G06F1714
CPC分类号： G06F17/142
摘要： A process circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2's compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a date pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.
摘要翻译：公开了一种用于计算快速傅里叶变换（FFT）的处理电路。在一个实施例中，处理电路包括一个存储器件，一个乘法器，一个检测器，一个状态机以及一个用于执行2的系数的补偿的电路。存储器存储设备存储数据值和系数（或旋转）值。检测器将日期指针与状态机集成。检测器设计用于识别对称线（通过存储器地址）。状态机当被检测器通知已经遇到对称线时，适当地调整系数，虚拟符号或输入到乘法器的真实符号。

4. 发明授权

US06065127A Multi-mode buffer for digital signal processor 失效
标题翻译：用于数字信号处理器的多模式缓冲器
公开(公告)号：US06065127A
公开(公告)日：2000-05-16
申请号：US152441
申请日：1998-09-14
申请人： Yair Aizenberg , Daniel Amrany
发明人： Yair Aizenberg , Daniel Amrany
IPC分类号： G06F9/38 , G06F13/38
CPC分类号： G06F9/3869
摘要： The present invention is generally directed to a multi-mode buffer that is configurable to control output delivered to an input, with a variable clock cycle delay. For example, the buffer may be controlled, in one mode to deliver input data to an output, at a one clock cycle delay (i.e., output data at next clock edge). In another mode, the buffer may be controlled to deliver input data to an output, at a two clock cycle delay. In accordance with one aspect of the present invention, the buffer includes a clock input, a data input, a control input, and an output. The input and the output may be of variable bit width. For example, 8 bits, 16 bits, or some other bit width. The buffer further includes circuitry for delivering data on the data input to the output in response to the clock input. In this regard, the buffer includes circuitry responsive to the control input to vary a delay in delivering the data input to the output, such that the delay may be one clock cycle, two clock cycles, or some other desired length.
摘要翻译：本发明一般涉及一种多模式缓冲器，其可配置为以可变的时钟周期延迟来控制传送到输入端的输出。例如，可以在一个时钟周期延迟（即在下一个时钟边沿输出数据）的一种模式中控制缓冲器以将输入数据传送到输出。在另一种模式中，缓冲器可以被控制，以两个时钟周期的延迟将输入数据传送到输出端。根据本发明的一个方面，缓冲器包括时钟输入，数据输入，控制输入和输出。输入和输出可以是可变的位宽。例如，8位，16位或其他位宽。缓冲器还包括用于响应于时钟输入将数据输入到输出端的数据输出的电路。在这方面，缓冲器包括响应于控制输入以改变将数据输入传送到输出的延迟的电路，使得延迟可以是一个时钟周期，两个时钟周期或一些其它期望的长度。

5. 发明授权

US06490672B1 Method for computing a fast fourier transform and associated circuit for addressing a data memory 有权
公开(公告)号：US06490672B1
公开(公告)日：2002-12-03
申请号：US09311964
申请日：1999-05-14
申请人： Yair Aizenberg , Yue-Peng Zheng
发明人： Yair Aizenberg , Yue-Peng Zheng
IPC分类号： G06F1200
CPC分类号： G06F17/142
摘要： The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way. More particularly, after computing a first set of complex butterfly operations (each having the same twiddle value) in a given computation stage, a first complex butterfly operation (having a different twiddle value) of a second set of complex butterfly operations, is computed in that stage. Thereafter, all remaining complex butterfly operations (having the same value) in that stage will be computed. This methodology will be repeated until all butterfly operations are calculated in each stage. An addressing circuit is also provided for addressing a data memory in a system for computing a FFT, the system having a data memory for storing data values and a coefficient memory for storing coefficient values.

6. 发明授权

US06662245B1 Apparatus and system for blocking memory access during DMA transfer 失效
标题翻译：用于在DMA传输期间阻止存储器访问的装置和系统
公开(公告)号：US06662245B1
公开(公告)日：2003-12-09
申请号：US09912993
申请日：2001-07-25
申请人： Yair Aizenberg , Laurent Alloin , Peter Kleewein , Yong Je Lim
发明人： Yair Aizenberg , Laurent Alloin , Peter Kleewein , Yong Je Lim
IPC分类号： G06F1314
CPC分类号： G06F13/28
摘要： The present invention is directed to an apparatus and system for selectively inhibiting access to a memory during a DMA block transfer. In accordance with one embodiment of the present invention, the system includes memory, a DMA engine, and logic configured so that when a control signal is asserted, the logic blocks the DMA engine's request for access to memory and generates an acknowledgment of the request, such that the DMA engine performs a DMA transfer without accessing data in memory.
摘要翻译：本发明涉及一种用于在DMA块传输期间选择性地禁止对存储器的访问的装置和系统。根据本发明的一个实施例，该系统包括存储器，DMA引擎和配置为使得当控制信号被断言时的逻辑，该逻辑阻止DMA引擎访问存储器的请求，并产生对该请求的确认，使得DMA引擎执行DMA传输而不访问存储器中的数据。

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