专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090249260A1 DESCRIPTION PROCESSING DEVICE, DESCRIPTION PROCESSING METHOD, AND RECORDING MEDIUM 有权
标题翻译：描述处理装置，描述处理方法和记录介质
公开(公告)号：US20090249260A1
公开(公告)日：2009-10-01
申请号：US12408209
申请日：2009-03-20
申请人： KAZUTOSHI WAKABAYASHI
发明人： KAZUTOSHI WAKABAYASHI
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A receiving unit 20 receiving a description expressing a finite state machine comprising states 0, 1, 2, . . . , N−1; a dividing unit 30 dividing the states 0, 1, 2, . . . , N−1 into groups 0, 1, 2, . . . , M−1, wherein the dividing unit allocates the states 0, 1, . . . , L[0]−1 to the group 0, allocates the states L[0], L[0]+1, . . . , L[1]−1 to the group 1, allocates the states L[1], L[1]+1, . . . , L[2]−1 to the group 2, . . . , and allocates the states L[M−2], L[M−2]+1, . . . , L[M−1]−1=N−1 to the group M−1, and a generating unit 40 generating a register transfer level description so that decoders which acquire the current state are generated for each group are provided.
摘要翻译：接收单元20接收表示包含状态0,1,2的有限状态机的描述。。。，N-1; 分割单元30分割状态0,1,2，...。。。，N-1组成组0,1,2。。。 M-1，其中分割单元分配状态0，1，...。。。，L [0] -1到组0，分配状态L [0]，L [0] +1。。。，L [1] -1到组1，分配状态L [1]，L [1] +1。。。，L [2] -1到组2。。。并分配状态L [M-2]，L [M-2] +1。。。产生组M-1的L [M-1] -1 = N-1，以及产生寄存器传送级别描述的生成单元40，以便为每组生成获取当前状态的解码器。

2. 发明授权

US06636925B1 Bus interface circuit preparation apparatus and recording medium 有权
标题翻译：总线接口电路准备设备和记录介质
公开(公告)号：US06636925B1
公开(公告)日：2003-10-21
申请号：US09686928
申请日：2000-10-11
申请人： Motohide Otsubo , Kazutoshi Wakabayashi , Yuichi Maruyama
发明人： Motohide Otsubo , Kazutoshi Wakabayashi , Yuichi Maruyama
IPC分类号： G06F1314
CPC分类号： G06F12/0646
摘要： An apparatus for automatically preparing a bus interface preparation apparatus is provided which is capable of preventing duplication of addresses of registers and memories. When data of a hardware description 10 are input into the extracting portion 101, the extracting portion 101 extracts from the data whether the memory element is a memory device or an FF. The extracting portion 101 reads the top address and the address size of the memory element when the memory is the memory element and reads address when the memory is an FF, and the thus read data are output to the address competition detecting portion 103. The address competition detecting portion 103 detects competition of the addresses by determining whether the address information stored in the bit data memory portion 102 includes 1. The output portion 104 converts the data concerning address of the memory into a description language of the hardware of the bus interface circuit.
摘要翻译：提供一种用于自动准备总线接口准备装置的装置，其能够防止寄存器和存储器的地址的重复。当将硬件描述10的数据输入到提取部分101中时，提取部分101从数据中提取存储器元件是存储器还是FF。当存储器是存储器元件时，提取部分101读取存储器元件的顶部地址和地址大小，并且当存储器是FF时读取地址，并且将这样读取的数据输出到地址竞争检测部分103.地址竞争检测部分103通过确定存储在比特数据存储部分102中的地址信息是否包括1来检测地址的竞争。输出部分104将关于存储器的地址的数据转换为总线接口电路的硬件的描述语言。

3. 发明授权

US08250502B2 Automated synthesis apparatus and method 有权
标题翻译：自动合成装置及方法
公开(公告)号：US08250502B2
公开(公告)日：2012-08-21
申请号：US11864623
申请日：2007-09-28
申请人： Kazutoshi Wakabayashi
发明人： Kazutoshi Wakabayashi
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is an automated synthesis system in which a generalized condition vector (GCV) is generated at a node that is the leaf of a tree indicating a conditional branch of a control/data flow graph representing the flow of behavioral control and data of a circuit. The GVC is a condition vector includes valid bits that are set as a condition vector of code 1 only at one component in a case where an outer conditional operation to a certain operation node is unresolved and, moreover, an inner conditional operation to said certain operation node is resolved, the valid bits being bits at positions where components of a vector of the inner side resolved conditional operation are 1's. The GVC of the operation node is calculated by taking a bitwise logical OR with the condition vector of the unresolved conditional operation. At such time the bits of component 1's of valid bits of the GVC of the inside resolved condition are masked in the bitwise logical OR operation, and parallel IF statements are treated the same as speculative execution of a condition.
摘要翻译：公开了一种自动化合成系统，其中在作为树的叶的节点处生成广义条件向量（GCV），其指示表示行为控制和电路数据的控制/数据流图的条件分支。 GVC是条件向量，包括在对某个操作节点进行外部条件操作未解决的情况下，仅在一个部件被设置为代码1的条件向量的有效位，并且还包括对所述特定操作的内部条件操作节点被解析，有效位是在内侧解析条件操作的向量的分量为1的位置处的位。通过对未解决的条件操作的条件向量进行按位逻辑OR来计算运算节点的GVC。在这样的时刻，内部解析条件的GVC的有效位的组件1的位在逐位逻辑或运算中被屏蔽，并且将IF语句与处理条件的推测执行相同。

4. 发明申请

US20120096418A1 BEHAVIORAL SYNTHESIS APPARATUS, METHOD, AND PROGRAM HAVING TEST BENCH GENERATION FUNCTION 有权
标题翻译：具有测试台生成功能的行为综合设备，方法和程序
公开(公告)号：US20120096418A1
公开(公告)日：2012-04-19
申请号：US13336328
申请日：2011-12-23
申请人： Takashi TAKENAKA , Akira MUKAIYAMA , Kazutoshi WAKABAYASHI
发明人： Takashi TAKENAKA , Akira MUKAIYAMA , Kazutoshi WAKABAYASHI
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.
摘要翻译：公开了一种用于产生测试台的行为合成装置，其中可以在行为模拟和RTL模拟中使用相同的测试矢量。该装置包括输入应用/输出信号观测定时信号产生装置，用于产生输入应用定时信号，输出观测定时信号和用于输入应用定时信号和输出观测定时信号的逻辑电路; 测试台生成手段可以生成观察信号，应用输入和观察输出的测试台。

5. 发明授权

US08375376B2 Description processing device, description processing method, and recording medium 有权
标题翻译：描述处理装置，描述处理方法和记录介质
公开(公告)号：US08375376B2
公开(公告)日：2013-02-12
申请号：US12413138
申请日：2009-03-27
申请人： Kazutoshi Wakabayashi
发明人： Kazutoshi Wakabayashi
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/505
摘要： A description processing device has: a receiving unit which receives a behavior level description; a label-name generating unit which generates a label name; a label disposing unit which disposes a top label statement; an extracting unit which extracts an extracted label statement, a variable-name generating unit which generates a variable name; a replacing unit which replaces a statement immediately below the top label statement to the extracted label statement by a column of a conditional executable statement and an operation/assignment statement and replaces a jump statement for jumping to the extracted label statement by a column of an operation/assignment statement and a jump statement for jumping to the top label; a control unit which repeats the extraction, the generation of a new variable name, and the replacement; an inserting unit which inserts an operation/assignment statement; and an output unit which outputs the behavior level description.
摘要翻译：描述处理装置具有：接收单元，其接收行为级别描述; 生成标签名称的标签名生成部; 标签处理单位处理顶级标签声明; 提取单元，其提取提取的标签语句;生成变量名称的变量名称生成单元; 替换单元，其通过条件可执行语句和操作/赋值语句的列将顶部标签语句之下的语句替换为提取的标签语句，并且通过操作列替换跳转语句以跳转到提取的标签语句 / assignment语句和跳转到顶部标签的跳转语句; 重复提取的控制单元，新变量名的生成和替换; 插入操作/分配语句的插入单元; 以及输出单元，其输出行为级别描述。

6. 发明申请

US20080184180A1 BEHAVIORAL SYNTHESIS APPARATUS, METHOD, AND PROGRAM HAVING TEST BENCH GENERATION FUNCTION 有权
标题翻译：具有测试台生成功能的行为综合设备，方法和程序
公开(公告)号：US20080184180A1
公开(公告)日：2008-07-31
申请号：US12022573
申请日：2008-01-30
申请人： Takashi TAKENAKA , Akira MUKAIYAMA , Kazutoshi WAKABAYASHI
发明人： Takashi TAKENAKA , Akira MUKAIYAMA , Kazutoshi WAKABAYASHI
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.
摘要翻译：公开了一种用于产生测试台的行为合成装置，其中可以在行为模拟和RTL模拟中使用相同的测试矢量。该装置包括输入应用/输出信号观测定时信号产生装置，用于产生输入应用定时信号，输出观测定时信号和用于输入应用定时信号和输出观测定时信号的逻辑电路; 测试台生成手段可以生成观察信号，应用输入和观察输出的测试台。

7. 发明申请

US20080082805A1 AUTOMATED SYNTHESIS APPARATUS AND METHOD 有权
标题翻译：自动合成装置及方法
公开(公告)号：US20080082805A1
公开(公告)日：2008-04-03
申请号：US11864623
申请日：2007-09-28
申请人： Kazutoshi WAKABAYASHI
发明人： Kazutoshi WAKABAYASHI
IPC分类号： G06F9/00
CPC分类号： G06F17/505
摘要： Disclosed is an automated synthesis system in which a generalized condition vector (GCV) is generated at a node that is the leaf of a tree indicating a conditional branch of a control/data flow graph representing the flow of behavioral control and data of a circuit. The GVC is a condition vector includes valid bits that are set as a condition vector of code 1 only at one component in a case where an outer conditional operation to a certain operation node is unresolved and, moreover, an inner conditional operation to said certain operation node is resolved, the valid bits being bits at positions where components of a vector of the inner side resolved conditional operation are 1's. The GVC of the operation node is calculated by taking a bitwise logical OR with the condition vector of the unresolved conditional operation. At such time the bits of component 1's of valid bits of the GVC of the inside resolved condition are masked in the bitwise logical OR operation, and parallel IF statements are treated the same as speculative execution of a condition.
摘要翻译：公开了一种自动化合成系统，其中在作为树的叶的节点处生成广义条件向量（GCV），其指示表示行为控制和电路数据的控制/数据流图的条件分支。 GVC是条件向量，包括在对某个操作节点进行外部条件操作未解决的情况下，仅在一个部件被设置为代码1的条件向量的有效位，并且还包括对所述特定操作的内部条件操作节点被解析，有效位是在内侧解析条件操作的向量的分量为1的位置处的位。通过对未解决的条件操作的条件向量进行按位逻辑OR来计算运算节点的GVC。在这样的时刻，内部解析条件的GVC的有效位的组件1的位在逐位逻辑或运算中被屏蔽，并且将IF语句与处理条件的推测执行相同。

8. 发明授权

US08386973B2 Behavioral synthesis apparatus, method, and program having test bench generation function 有权
标题翻译：具有测试台生成功能的行为综合装置，方法和程序
公开(公告)号：US08386973B2
公开(公告)日：2013-02-26
申请号：US13336328
申请日：2011-12-23
申请人： Takashi Takenaka , Akira Mukaiyama , Kazutoshi Wakabayashi
发明人： Takashi Takenaka , Akira Mukaiyama , Kazutoshi Wakabayashi
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.
摘要翻译：公开了一种用于产生测试台的行为合成装置，其中可以在行为模拟和RTL模拟中使用相同的测试矢量。该装置包括输入应用/输出信号观测定时信号产生装置，用于产生输入应用定时信号，输出观测定时信号和用于输入应用定时信号和输出观测定时信号的逻辑电路; 测试台生成手段可以生成观察信号，应用输入和观察输出的测试台。

9. 发明授权

US08108808B2 Description processing device, description processing method, and recording medium 有权
标题翻译：描述处理装置，描述处理方法和记录介质
公开(公告)号：US08108808B2
公开(公告)日：2012-01-31
申请号：US12408209
申请日：2009-03-20
申请人： Kazutoshi Wakabayashi
发明人： Kazutoshi Wakabayashi
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A receiving unit receiving a description expressing a finite state machine comprising states 0, 1, 2, . . . , N−1; a dividing unit dividing the states 0, 1, 2, . . . , N−1 into groups 0, 1, 2, . . . , M−1, wherein the dividing unit allocates the states 0, 1, . . . , L[0]−1 to the group 0, allocates the states L[0], L[0]+1, . . . , L[1]−1 to the group 1, allocates the states L[1], L[1]+1, . . . , L[2]−1 to the group 2, . . . , and allocates the states L[M−2], L[M−2]+1, . . . , L[M−1]−1=N−1 to the group M−1; and a generating unit generating a register transfer level description so that decoders which acquire the current state are generated for each group are provided.
摘要翻译：接收单元接收表示包含状态0,1,2的有限状态机的描述。。。，N-1; 分割单元分割状态0,1,2，...。。。，N-1组成组0,1,2。。。 M-1，其中分割单元分配状态0，1，...。。。，L [0] -1到组0，分配状态L [0]，L [0] +1。。。，L [1] -1到组1，分配状态L [1]，L [1] +1。。。，L [2] -1到组2。。。并分配状态L [M-2]，L [M-2] +1。。。，对于M-1族，L [M-1] -1 = N-1; 以及生成单元，生成寄存器传送级别描述，从而为每组生成获取当前状态的解码器。

10. 发明授权

US08091051B2 Behavioral synthesis apparatus, method, and program having test bench generation function 有权
标题翻译：具有测试台生成功能的行为综合装置，方法和程序
公开(公告)号：US08091051B2
公开(公告)日：2012-01-03
申请号：US12022573
申请日：2008-01-30
申请人： Takashi Takenaka , Akira Mukaiyama , Kazutoshi Wakabayashi
发明人： Takashi Takenaka , Akira Mukaiyama , Kazutoshi Wakabayashi
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.
摘要翻译：公开了一种用于产生测试台的行为合成装置，其中可以在行为模拟和RTL模拟中使用相同的测试矢量。该装置包括输入应用/输出信号观测定时信号产生装置，用于产生输入应用定时信号，输出观测定时信号和用于输入应用定时信号和输出观测定时信号的逻辑电路; 测试台生成手段可以生成观察信号，应用输入和观察输出的测试台。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式