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31. 发明申请

US20060083098A1 Electronic memory with binary storage elements 失效
标题翻译：具有二进制存储元件的电子存储器
公开(公告)号：US20060083098A1
公开(公告)日：2006-04-20
申请号：US11292741
申请日：2005-12-02
申请人： Iu-Meng Ho
发明人： Iu-Meng Ho
IPC分类号： G11C8/00
CPC分类号： G11C11/56 , G11C7/1006 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C11/16 , G11C11/22 , G11C11/4094 , G11C11/4097 , G11C11/5607 , G11C11/5621 , G11C11/565 , G11C11/5657 , G11C11/5678 , G11C13/0004 , G11C16/0408 , G11C16/0416 , G11C16/0441 , G11C16/0491 , G11C2211/4013 , G11C2211/5641 , H01L29/785
摘要： An electronic memory using true and complementary dual bit lines and dual binary storage elements cell architecture comprising a memory cell pair with four binary storage elements with each memory cell pair capable of existing in up to sixteen electronic memory states. The four binary storage elements together, normally used to store two true and complementary data bits, are used to store two, three, or four data bits depending on the noise margin allowed and bit width selection. The memory can be ferroelectric memory FeRAM, a flash memory, a ROM, a dynamic memory DRAM, an OUM, a MRAM, a NAND memory, or a NOR memory.
摘要翻译：一种使用真实且互补的双位线和双二进制存储元件的电子存储器单元架构，其包括具有四个二进制存储元件的存储器单元对，每个存储器单元对能够存在多达十六个电子存储器状态。通常用于存储两个真实和互补数据位的四个二进制存储元件一起用于存储两个，三个或四个数据位，这取决于允许的噪声容限和位宽选择。存储器可以是铁电存储器FeRAM，闪速存储器，ROM，动态存储器DRAM，OUM，MRAM，NAND存储器或NOR存储器。

32. 发明申请

US20050162890A1 Ferroelectric storage device 失效
标题翻译：铁电存储设备
公开(公告)号：US20050162890A1
公开(公告)日：2005-07-28
申请号：US11041251
申请日：2005-01-25
申请人： Takayoshi Yamada , Yoshihisa Kato
发明人： Takayoshi Yamada , Yoshihisa Kato
IPC分类号： G11C11/22 , G11C11/56
CPC分类号： G11C11/5657 , G11C11/22
摘要： In the present invention, a polarization having a lower polarization level than a saturation polarization is caused in a ferroelectric capacitor by applying a voltage that is lower than a saturation voltage to the ferroelectric capacitor. This allows a storage device to store many values by changing a length of a write-time during which the voltage is applied to the capacitor.
摘要翻译：在本发明中，通过向铁电电容器施加低于饱和电压的电压，在铁电电容器中产生具有比饱和极化低的极化电平的极化。这允许存储设备通过改变将电压施加到电容器的写入时间的长度来存储许多值。

33. 发明申请

US20050063225A1 Semiconductor memory device and various systems mounting them 有权
标题翻译：半导体存储器件和各种系统的安装
公开(公告)号：US20050063225A1
公开(公告)日：2005-03-24
申请号：US10963820
申请日：2004-10-14
申请人： Daisaburo Takashima
发明人： Daisaburo Takashima
IPC分类号： G11C11/22 , G11C11/56 , H01L27/115 , G11C7/00
CPC分类号： H01L27/11502 , G11C11/22 , G11C11/5657
摘要： A semiconductor memory device comprises a plurality of memory cells each having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal, wherein the plurality of memory cells are connected in series, and one or more selected transistors connected to at least one terminal of the series connected memory cells to constitute a memory cell block, the memory cell block having one terminal connected to a bitline and another terminal connected to a plate electrode, and wherein two memory cell blocks, which are respectively connected to two bit lines forming a bit line pair and also connected to the same word line, are respectively connected to a first plate electrode and a second plate electrode.
摘要翻译：半导体存储器件包括多个存储单元，每个存储单元具有源极端子和漏极端子以及具有连接到源极端子的第一端子的铁电电容器，其中多个存储器单元串联连接，并且一个或多个选择的晶体管连接到所述串联连接的存储单元的至少一个端子以构成存储单元块，所述存储单元块具有连接到位线的一个端子和连接到平板电极的另一端子，并且其中分别连接的两个存储单元块形成位线对并且也连接到相同字线的两个位线分别连接到第一板电极和第二板电极。

34. 发明申请

US20050052896A1 NONVOLATILE FERROELECTRIC MEMORY DEVICE HAVING MULTI-BIT CONTROL FUNCTION 有权
标题翻译：具有多位控制功能的非易失性存储器件
公开(公告)号：US20050052896A1
公开(公告)日：2005-03-10
申请号：US10742395
申请日：2003-12-22
申请人： Hee Kang
发明人： Hee Kang
IPC分类号： G11C7/14 , G11C11/22 , G11C11/56
CPC分类号： G11C11/5657 , G11C11/22
摘要： A nonvolatile ferroelectric memory device having a multi-bit control function can store and sense multi-bit data in a ferroelectric memory cell. In the memory device, a plurality of cell array blocks generates a plurality of different sensing critical voltages in a reference timing strobe interval. As a result, in different time intervals, the plurality of sensing critical voltages are compared with a plurality of cell data sensing voltages applied from a main bitline. A data register array unit stores a plurality of cell data applied from the plurality of cell array blocks in response to a plurality of read lock signals activated at different timings in different time intervals, respectively. Therefore, the plurality of data bits can be stored in a cell.
摘要翻译：具有多位控制功能的非易失性铁电存储器件可以存储和感测铁电存储单元中的多位数据。在存储装置中，多个单元阵列块在参考定时选通间隔中产生多个不同的感测临界电压。结果，在不同的时间间隔中，将多个感测临界电压与从主位线施加的多个单元数据感测电压进行比较。数据寄存器阵列单元响应于分别以不同时间间隔在不同定时激活的多个读锁定信号，存储从多个单元阵列块施加的多个单元数据。因此，多个数据位可以存储在单元中。

35. 发明申请

US20040090812A1 Semiconductor memory device and various system mounting them 失效
标题翻译：半导体存储器件和各种系统的安装
公开(公告)号：US20040090812A1
公开(公告)日：2004-05-13
申请号：US10691706
申请日：2003-10-24
发明人： Daisaburo Takashima
IPC分类号： G11C011/22
CPC分类号： H01L27/11502 , G11C11/22 , G11C11/5657
摘要： A semiconductor memory device comprises a plurality of memory cells each having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal, wherein the plurality of memory cells are connected in series, and one or more selected transistors connected to at least one terminal of the series connected memory cells to constitute a memory cell block, the memory cell block having one terminal connected to a bitline and another terminal connected to a plate electrode, and wherein two memory cell blocks, which are respectively connected to two bit lines forming a bit line pair and also connected to the same word line, are respectively connected to a first plate electrode and a second plate electrode.
摘要翻译：半导体存储器件包括多个存储单元，每个存储单元具有源极端子和漏极端子以及具有连接到源极端子的第一端子的铁电电容器，其中多个存储器单元串联连接，并且一个或多个选择的晶体管连接到所述串联连接的存储单元的至少一个端子以构成存储单元块，所述存储单元块具有连接到位线的一个端子和连接到平板电极的另一端子，并且其中分别连接的两个存储单元块形成位线对并且也连接到相同字线的两个位线分别连接到第一板电极和第二板电极。

36. 发明授权

US06605839B2 Multi-level type nonvolatile semiconductor memory device 有权
公开(公告)号：US06605839B2
公开(公告)日：2003-08-12
申请号：US10303726
申请日：2002-11-26
申请人： Hirotomo Miura , Yasuo Sato
发明人： Hirotomo Miura , Yasuo Sato
IPC分类号： H01L2976
CPC分类号： H01L27/11568 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/5657 , G11C11/5671 , G11C16/0466 , H01L27/115 , H01L29/7923
摘要： A nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells including a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in the semiconductor substrate, an electric charge-capturing film formed on a channel region between the pair of source and drain regions, and a gate electrode formed on the charge-capturing film and working as a control electrode. The electric charge-capturing film has a multi-layer structure in which at least four insulating films and at least three dielectric films each working as an electric charge accumulation layer are alternatingly laminated one upon the other, the lowermost insulating film among the at least four insulating films is formed as a gate-insulating film, a plurality of different threshold voltages are set to the at least three dielectric films to correspond to their electric charge-capturing states, and at least four kinds of memory states are specified depending upon the plurality of threshold voltages. This constitution makes it possible to easily and reliably adjust the amount of electric charge to be captured and, hence, to store desired multi-value data while preventing the occurrence of an inconvenience such as data corruption.

37. 发明申请

US20030112650A1 Nonvolatile ferroelectric memory device and method for storing multiple bit using the same 有权
标题翻译：非易失性铁电存储器件和使用其存储多个位的方法
公开(公告)号：US20030112650A1
公开(公告)日：2003-06-19
申请号：US10317150
申请日：2002-12-12
发明人： Hee Bok Kang
IPC分类号： G11C011/22
CPC分类号： G11C11/5657 , G11C7/06 , G11C11/22
摘要： A nonvolatile ferroelectric memory device and a method for writing and reading multiple-bit data using the same, in which multiple bit data is stored in one cell to reduce a cell layout area, thereby obtaining price competitiveness of a chip. The nonvolatile ferroelectric memory device includes a sensing amplifier block having multiple sensing amplifiers comparing multiple-level signals from main bitlines and sensing them in a multiple-bit, the sensing amplifiers being commonly used in a multiple cell array blocks to feed the sensed multiple-bit levels back and restore them in a cell, and switching transistors arranged one by one per sub bitline to sense data values of the unit cell.
摘要翻译：非易失性铁电存储器件以及使用该非易失性铁电存储器件的多位数据的读取和读取方法，其中多个位数据存储在一个单元中以减少单元布局区域，从而获得芯片的价格竞争力。非易失性铁电存储器件包括具有多个感测放大器的感测放大器模块，其将来自主位线的多电平信号与多位信号进行比较，所述感测放大器通常用于多单元阵列块以馈送所感测的多位在单元格中恢复并恢复它们，并且每个子位线逐个排列的晶体管被切换以感测单位单元的数据值。

38. 发明授权

US06574134B1 Non-volatile ferroelectric capacitor memory circuit having nondestructive read capability 有权
标题翻译：具有非破坏性读取能力的非挥发性铁电电容器存储电路
公开(公告)号：US06574134B1
公开(公告)日：2003-06-03
申请号：US10050153
申请日：2002-01-18
申请人： Shue-Shuen Chen , Hsiang-Lan Lung
发明人： Shue-Shuen Chen , Hsiang-Lan Lung
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C11/5657
摘要： A non-destructive ferroelectric capacitor-based memory circuit has a plurality of word lines located in parallel to each other. A plurality of bit lines is located across the word lines and a plurality of memory cells is located at intersections between the word lines and the bit lines. Each of the memory cells further has a MOS transistor and two ferroelectric capacitors coupled together in series to have a common node to couple with the transistor, and two plate lines coupled with two non-common nodes of the two series ferroelectric capacitors, respectively.
摘要翻译：非破坏性的基于铁电电容器的存储器电路具有彼此平行地定位的多个字线。多个位线位于字线之间，并且多个存储单元位于字线和位线之间的交叉处。每个存储单元还具有串联耦合在一起的MOS晶体管和两个铁电电容器，以分别具有与晶体管耦合的公共节点，以及分别与两个串联铁电电容器的两个非共同节点耦合的两个板线。

39. 发明申请

US20030058701A1 Semiconductor memory device and various systems mounting them 有权
公开(公告)号：US20030058701A1
公开(公告)日：2003-03-27
申请号：US10225239
申请日：2002-08-22
发明人： Daisaburo Takashima
IPC分类号： G11C007/00
CPC分类号： H01L27/11502 , G11C11/22 , G11C11/5657
摘要： A semiconductor memory device comprises a plurality of memory cells each having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal, wherein the plurality of memory cells are connected in series, and one or more selected transistors connected to at least one terminal of the series connected memory cells to constitute a memory cell block, the memory cell block having one terminal connected to a bitline and another terminal connected to a plate electrode, and wherein two memory cell blocks, which are respectively connected to two bit lines forming a bit line pair and also connected to the same word line, are respectively connected to a first plate electrode and a second plate electrode.

40. 发明授权

US06469343B1 Multi-level type nonvolatile semiconductor memory device 有权
标题翻译：多级型非易失性半导体存储器件
公开(公告)号：US06469343B1
公开(公告)日：2002-10-22
申请号：US09679650
申请日：2000-10-05
申请人： Hirotomo Miura , Yasuo Sato
发明人： Hirotomo Miura , Yasuo Sato
IPC分类号： H01L29792
CPC分类号： H01L27/11568 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/5657 , G11C11/5671 , G11C16/0466 , H01L27/115 , H01L29/7923
摘要： A nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells including a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in the semiconductor substrate, an electric charge-capturing film formed on a channel region between the pair of source and drain regions, and a gate electrode formed on the charge-capturing film and working as a control electrode. The electric charge-capturing film has a multi-layer structure in which at least four insulating films and at least three dielectric films each working as an electric charge accumulation layer are alternatingly laminated one upon the other, the lowermost insulating film among the at least four insulating films is formed as a gate-insulating film, a plurality of different threshold voltages are set to the at least three dielectric films to correspond to their electric charge-capturing states, and at least four kinds of memory states are specified depending upon the plurality of threshold voltages. This constitution makes it possible to easily and reliably adjust the amount of electric charge to be captured and, hence, to store desired multi-value data while preventing the occurrence of an inconvenience such as data corruption.
摘要翻译：一种具有非易失性存储单元的非易失性半导体存储器件，每个所述存储单元包括一种类型的导电的半导体衬底，形成在所述半导体衬底中的相对电导体的一对源区和漏区，在一对源区和漏区之间的沟道区上形成的捕获膜，以及形成在电荷捕获膜上并用作控制电极的栅电极。电荷捕获膜具有多层结构，其中至少四个绝缘膜和每个用作电荷蓄积层的至少三个电介质膜彼此交替层叠，所述至少四个绝缘膜形成绝缘膜作为栅极绝缘膜，对至少三个电介质膜设置多个不同的阈值电压以对应于其电荷捕获状态，并且根据多个不同的阈值电压指定至少四种存储状态的阈值电压。这种结构使得可以容易且可靠地调整要捕获的电荷量，并因此存储期望的多值数据，同时防止诸如数据损坏的不便的发生。

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