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1. 发明授权

US06605839B2 Multi-level type nonvolatile semiconductor memory device 有权
公开(公告)号：US06605839B2
公开(公告)日：2003-08-12
申请号：US10303726
申请日：2002-11-26
申请人： Hirotomo Miura , Yasuo Sato
发明人： Hirotomo Miura , Yasuo Sato
IPC分类号： H01L2976
CPC分类号： H01L27/11568 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/5657 , G11C11/5671 , G11C16/0466 , H01L27/115 , H01L29/7923
摘要： A nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells including a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in the semiconductor substrate, an electric charge-capturing film formed on a channel region between the pair of source and drain regions, and a gate electrode formed on the charge-capturing film and working as a control electrode. The electric charge-capturing film has a multi-layer structure in which at least four insulating films and at least three dielectric films each working as an electric charge accumulation layer are alternatingly laminated one upon the other, the lowermost insulating film among the at least four insulating films is formed as a gate-insulating film, a plurality of different threshold voltages are set to the at least three dielectric films to correspond to their electric charge-capturing states, and at least four kinds of memory states are specified depending upon the plurality of threshold voltages. This constitution makes it possible to easily and reliably adjust the amount of electric charge to be captured and, hence, to store desired multi-value data while preventing the occurrence of an inconvenience such as data corruption.

2. 发明授权

US06469343B1 Multi-level type nonvolatile semiconductor memory device 有权
标题翻译：多级型非易失性半导体存储器件
公开(公告)号：US06469343B1
公开(公告)日：2002-10-22
申请号：US09679650
申请日：2000-10-05
申请人： Hirotomo Miura , Yasuo Sato
发明人： Hirotomo Miura , Yasuo Sato
IPC分类号： H01L29792
CPC分类号： H01L27/11568 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/5657 , G11C11/5671 , G11C16/0466 , H01L27/115 , H01L29/7923
摘要： A nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells including a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in the semiconductor substrate, an electric charge-capturing film formed on a channel region between the pair of source and drain regions, and a gate electrode formed on the charge-capturing film and working as a control electrode. The electric charge-capturing film has a multi-layer structure in which at least four insulating films and at least three dielectric films each working as an electric charge accumulation layer are alternatingly laminated one upon the other, the lowermost insulating film among the at least four insulating films is formed as a gate-insulating film, a plurality of different threshold voltages are set to the at least three dielectric films to correspond to their electric charge-capturing states, and at least four kinds of memory states are specified depending upon the plurality of threshold voltages. This constitution makes it possible to easily and reliably adjust the amount of electric charge to be captured and, hence, to store desired multi-value data while preventing the occurrence of an inconvenience such as data corruption.
摘要翻译：一种具有非易失性存储单元的非易失性半导体存储器件，每个所述存储单元包括一种类型的导电的半导体衬底，形成在所述半导体衬底中的相对电导体的一对源区和漏区，在一对源区和漏区之间的沟道区上形成的捕获膜，以及形成在电荷捕获膜上并用作控制电极的栅电极。电荷捕获膜具有多层结构，其中至少四个绝缘膜和每个用作电荷蓄积层的至少三个电介质膜彼此交替层叠，所述至少四个绝缘膜形成绝缘膜作为栅极绝缘膜，对至少三个电介质膜设置多个不同的阈值电压以对应于其电荷捕获状态，并且根据多个不同的阈值电压指定至少四种存储状态的阈值电压。这种结构使得可以容易且可靠地调整要捕获的电荷量，并因此存储期望的多值数据，同时防止诸如数据损坏的不便的发生。

3. 发明授权

US5932917A Input protective circuit having a diffusion resistance layer 失效
标题翻译：具有扩散电阻层的输入保护电路
公开(公告)号：US5932917A
公开(公告)日：1999-08-03
申请号：US834840
申请日：1997-04-10
申请人： Hirotomo Miura
发明人： Hirotomo Miura
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0288 , H01L27/0259
摘要： An input protective circuit includes a resistance element for connecting the input terminal and internal circuit of a semiconductor integrated circuit, and a field effect transistor for discharging a surge input to the ground potential. Adjacent diffusion layer regions consisting of a diffusion resistance layer corresponding to the resistance element and an impurity diffusion layer corresponding to the drain or source of the field effect transistor and connected adjacent to each other are formed by double diffusion using ion implantation.
摘要翻译：输入保护电路包括用于连接半导体集成电路的输入端和内部电路的电阻元件和用于将浪涌输入放电到地电位的场效应晶体管。通过使用离子注入的双扩散形成由与电阻元件对应的扩散电阻层和对应于场效应晶体管的漏极或源极相互连接的相邻扩散层区域。

4. 发明授权

US06596590B1 Method of making multi-level type non-volatile semiconductor memory device 有权
标题翻译：制造多级型非易失性半导体存储器件的方法
公开(公告)号：US06596590B1
公开(公告)日：2003-07-22
申请号：US09679649
申请日：2000-10-05
申请人： Hirotomo Miura , Yasuo Sato
发明人： Hirotomo Miura , Yasuo Sato
IPC分类号： H01L218247
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/5657 , G11C11/5671 , G11C16/0466 , H01L27/115 , H01L27/11568 , H01L29/7923
摘要： A nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells including a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in the semiconductor substrate, an electric charge-capturing film formed on a channel region between the pair of source and drain regions, and a gate electrode formed on the charge-capturing film and working as a control electrode. The electric charge-capturing film has a multi-layer structure in which at least four insulating films and at least three dielectric films each working as an electric charge accumulation layer are alternatingly laminated one upon the other, the lowermost insulating film among the at least four insulating films is formed as a gate-insulating film, a plurality of different threshold voltages are set to the at least three dielectric films to correspond to their electric charge-capturing states, and at least four kinds of memory states are specified depending upon the plurality of threshold voltages. This constitution makes it possible to easily and reliably adjust the amount of electric charge to be captured and, hence, to store desired multi-value data while preventing the occurrence of an inconvenience such as data corruption.
摘要翻译：一种具有非易失性存储单元的非易失性半导体存储器件，每个所述存储单元包括一种类型的导电的半导体衬底，形成在所述半导体衬底中的相对电导体的一对源区和漏区，在一对源区和漏区之间的沟道区上形成的捕获膜，以及形成在电荷捕获膜上并用作控制电极的栅电极。电荷捕获膜具有多层结构，其中至少四个绝缘膜和每个用作电荷蓄积层的至少三个电介质膜彼此交替层叠，所述至少四个绝缘膜形成绝缘膜作为栅极绝缘膜，对至少三个电介质膜设置多个不同的阈值电压以对应于其电荷捕获状态，并且根据多个不同的阈值电压指定至少四种存储状态的阈值电压。这种结构使得可以容易且可靠地调整要捕获的电荷量，并因此存储期望的多值数据，同时防止诸如数据损坏的不便的发生。

5. 发明授权

US06800911B2 Method of making a polycide interconnection layer having a silicide film formed on a polycrystal silicon for a semiconductor device 有权
标题翻译：制造在半导体器件的多晶硅上形成硅化物膜的多晶硅互连层的方法
公开(公告)号：US06800911B2
公开(公告)日：2004-10-05
申请号：US10447962
申请日：2003-05-30
申请人： Hirotomo Miura
发明人： Hirotomo Miura
IPC分类号： H01L2976
CPC分类号： H01L29/42324 , H01L21/28035 , H01L21/28052 , H01L21/28061 , H01L21/28273 , H01L29/4925 , H01L29/7881
摘要： A semiconductor device has a semiconductor substrate and a conductive layer formed above the semiconductor substrate. The conductive layer has a silicon film, a silicide film formed on the silicon film, and a high melting-point metal film formed on the silicide film. The silicon film has a non-doped layer, which does not contain impurities, and an impurity layer which is formed on the non-doped layer and contains impurities. The silicide film is formed on the impurity layer of the silicon film.
摘要翻译：半导体器件具有半导体衬底和形成在半导体衬底之上的导电层。导电层具有硅膜，形成在硅膜上的硅化物膜和在硅化物膜上形成的高熔点金属膜。硅膜具有不含杂质的非掺杂层和形成在非掺杂层上并含有杂质的杂质层。硅化物膜形成在硅膜的杂质层上。

6. 发明授权

US06649542B2 Multi-level type nonvolatile semiconductor memory device 有权
标题翻译：多级型非易失性半导体存储器件
公开(公告)号：US06649542B2
公开(公告)日：2003-11-18
申请号：US10146949
申请日：2002-05-17
申请人： Hirotomo Miura , Yasuo Sato
发明人： Hirotomo Miura , Yasuo Sato
IPC分类号： H01L21469
CPC分类号： H01L27/11568 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/5657 , G11C11/5671 , G11C16/0466 , H01L27/115 , H01L29/7923
摘要： A method of writing data into a memory cell of a non-volatile semiconductor memory device includes setting a write voltage applied to portions of the memory cells depending upon a value of write data, and applying, to a gate electrode, a voltage by which an electric charge is allowed to tunnel through an insulating film on a lower side of a dialectric film that captures the electric charge corresponding to a data value. The amount of electric charge captured is easily and reliably adjusted in order to store desired multi-value digital data, while preventing occurrence of data corruption.
摘要翻译：将数据写入到非易失性半导体存储器件的存储单元中的方法包括根据写入数据的值来设置施加到存储器单元的部分的写入电压，以及向栅极施加电压，允许电荷通过捕获对应于数据值的电荷的方位膜的下侧的绝缘膜隧穿。捕获的电荷量容易且可靠地调整以便存储所需的多值数字数据，同时防止数据损坏的发生。

7. 发明授权

US06285596B1 Multi-level type nonvolatile semiconductor memory device 有权
标题翻译：多级型非易失性半导体存储器件
公开(公告)号：US06285596B1
公开(公告)日：2001-09-04
申请号：US09679651
申请日：2000-10-05
申请人： Hirotomo Miura , Yasuo Sato
发明人： Hirotomo Miura , Yasuo Sato
IPC分类号： G11C1604
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/5657 , G11C11/5671 , G11C16/0466 , H01L27/115 , H01L27/11568 , H01L29/7923
摘要： A nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells including a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in the semiconductor substrate, an electric charge-capturing film formed on a channel region between the pair of source and drain regions, and a gate electrode formed on the charge-capturing film and working as a control electrode. The electric charge-capturing film has a multi-layer structure in which at least four insulating films and at least three dielectric films each working as an electric charge accumulation layer are alternatingly laminated one upon the other, the lowermost insulating film among the at least four insulating films is formed as a gate-insulating film, a plurality of different threshold voltages are set to the at least three dielectric films to correspond to their electric charge-capturing states, and at least four kinds of memory states are specified depending upon the plurality of threshold voltages. This constitution makes it possible to easily and reliably adjust the amount of electric charge to be captured and, hence, to store desired multi-value data while preventing the occurrence of an inconvenience such as data corruption.
摘要翻译：一种具有非易失性存储单元的非易失性半导体存储器件，每个所述存储单元包括一种类型的导电的半导体衬底，形成在所述半导体衬底中的相对电导体的一对源区和漏区，在一对源区和漏区之间的沟道区上形成的捕获膜，以及形成在电荷捕获膜上并用作控制电极的栅电极。电荷捕获膜具有多层结构，其中至少四个绝缘膜和每个用作电荷蓄积层的至少三个电介质膜彼此交替层叠，所述至少四个绝缘膜形成绝缘膜作为栅极绝缘膜，对至少三个电介质膜设置多个不同的阈值电压以对应于其电荷捕获状态，并且根据多个不同的阈值电压指定至少四种存储状态的阈值电压。这种结构使得可以容易且可靠地调整要捕获的电荷量，并因此存储期望的多值数据，同时防止诸如数据损坏的不便的发生。

8. 发明授权

US06208003B1 Semiconductor structure provided with a polycide interconnection layer having a silicide film formed on a polycrystal silicon film 失效
标题翻译：具有在多晶硅膜上形成有硅化物膜的多晶硅互连层的半导体结构
公开(公告)号：US06208003B1
公开(公告)日：2001-03-27
申请号：US09116955
申请日：1998-07-17
申请人： Hirotomo Miura
发明人： Hirotomo Miura
IPC分类号： H01L31119
CPC分类号： H01L29/42324 , H01L21/28035 , H01L21/28052 , H01L21/28061 , H01L21/28273 , H01L29/4925 , H01L29/7881
摘要： A semiconductor device has a semiconductor substrate and a conductive layer formed above the semiconductor substrate. The conductive layer has a silicon film, a silicide film formed on the silicon film, and a high melting-point metal film formed on the silicide film. The silicon film has a non-doped layer, which does not contain impurities, and an impurity layer which is formed on the non-doped layer and contains impurities. The silicide film is formed on the impurity layer of the silicon film.
摘要翻译：半导体器件具有半导体衬底和形成在半导体衬底之上的导电层。导电层具有硅膜，形成在硅膜上的硅化物膜和在硅化物膜上形成的高熔点金属膜。硅膜具有不含杂质的非掺杂层和形成在非掺杂层上并含有杂质的杂质层。硅化物膜形成在硅膜的杂质层上。

9. 发明授权

US06596567B1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A IMPURITY LAYER DISPOSED BETWEEN A NON-DOPED SILICON FILM AND HIGH MELTING-POINT METAL FILM FOR REDUCING SOLID STATE REACTION BETWEEN SAID HIGH MELTING-POINT METAL FILM AND POLYCRYSTAL SILICON FILM 失效
标题翻译：用于制造具有非极性硅膜和高熔点金属膜之间的有害层的半导体器件的制造方法，用于减少高熔点金属膜和多晶硅膜之间的固态反应
公开(公告)号：US06596567B1
公开(公告)日：2003-07-22
申请号：US09710883
申请日：2000-11-14
申请人： Hirotomo Miura
发明人： Hirotomo Miura
IPC分类号： H01L21335
CPC分类号： H01L29/42324 , H01L21/28035 , H01L21/28052 , H01L21/28061 , H01L21/28273 , H01L29/4925 , H01L29/7881
摘要： A semiconductor device has a semiconductor substrate and a conductive layer formed above the semiconductor substrate. The conductive layer has a silicon film, a silicide film formed on the silicon film, and a high melting-point metal film formed on the silicide film. The silicon film has a non-doped layer, which does not contain impurities, and an impurity layer which is formed on the non-doped layer and contains impurities. The silicide film is formed on the impurity layer of the silicon film.
摘要翻译：半导体器件具有半导体衬底和形成在半导体衬底之上的导电层。导电层具有硅膜，形成在硅膜上的硅化物膜和在硅化物膜上形成的高熔点金属膜。硅膜具有不含杂质的非掺杂层和形成在非掺杂层上并含有杂质的杂质层。硅化物膜形成在硅膜的杂质层上。

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