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1. 发明申请

US20050174841A1 Electronic memory with tri-level cell pair 审中-公开
标题翻译：具有三电平电池对的电子存储器
公开(公告)号：US20050174841A1
公开(公告)日：2005-08-11
申请号：US11049236
申请日：2005-02-02
申请人： Iu-Meng Ho
发明人： Iu-Meng Ho
IPC分类号： G11C11/56 , G11C11/34
CPC分类号： G11C11/5607 , G11C7/1006 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/565 , G11C11/5657 , G11C11/5678 , G11C11/5692 , G11C13/0004 , G11C16/0483 , G11C29/00
摘要： An electronic memory comprising a memory cell pair with each memory cell capable of existing in three or more electronic memory states so that the pair is capable of existing in nine electronic states. The memory cell is capable of storing three data bits plus an extra state that can be used for data integrity. The memory can be a flash memory, an ROM, a dynamic memory, an OUM, an MRAM, an NAND memory or an NOR memory.
摘要翻译：一种电子存储器，包括具有能够以三个或更多个电子存储器状态存在的每个存储器单元的存储器单元对，使得该对能够以九个电子状态存在。存储单元能够存储三个数据位加上可用于数据完整性的额外状态。存储器可以是闪速存储器，ROM，动态存储器，OUM，MRAM，NAND存储器或NOR存储器。

2. 发明申请

US20070120261A1 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device 有权
标题翻译：电源和接地屏蔽网可以消除集成电路设备中路由的电容和电感信号耦合效应
公开(公告)号：US20070120261A1
公开(公告)日：2007-05-31
申请号：US11698330
申请日：2007-01-25
申请人： Iu-Meng Ho
发明人： Iu-Meng Ho
IPC分类号： H01L23/52
CPC分类号： H01L23/5286 , H01L23/5225 , H01L27/118 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid. A similar embodiment represents grid routing technique where the signals are routed between layers N and N+1. Another embodiment enables signals to be shielded by opposite power and ground grids on left, right, top and bottom. Additional embodiments also include utilization of similar mesh utilized in standard cell and/or in the gate array routing area or any other area where any other signal line is to be shielded.
摘要翻译：电源和接地屏蔽网格，用于消除集成电路设备中路由的电容和电感信号耦合效应。一个实施例描述了电源线和地线的屏蔽网路的布线，以消除由电容耦合和电感耦合产生的噪声。相对较长的信号线路路由在完全连接的电源和接地屏蔽网之间，这可能在信号路由阶段期间或在电力网状路由阶段期间由路由器生成。只剩下奇迹或偶数轨道进行信号路由，功率网（VDD）和地网（VSS）路由并完全互连，留下较短的段，从而降低电路设备的RC效应。另一个实施例提出了一种技术，其中使用用于无栅格布线的电力和地面网格来屏蔽信号。另一个实施例提出了一种多层网格路由技术，其中信号在均匀网格上布线，并且电力和地线在奇数网格上布线。类似的实施例表示网格路由技术，其中信号在层N和N + 1之间路由。另一个实施例使信号能够被左，右，上，下相反的电源和接地网屏蔽。另外的实施例还包括利用在标准单元中和/或门阵列布线区域或其它任何其它信号线被屏蔽的任何其它区域中使用的类似网格。

3. 发明申请

US20060187700A1 Single event effect (SEE) tolerant circuit design strategy for SOI type technology 审中-公开
标题翻译： SOI型技术的单事件效应（SEE）容限电路设计策略
公开(公告)号：US20060187700A1
公开(公告)日：2006-08-24
申请号：US11350673
申请日：2006-02-08
申请人： Iu-Meng Ho
发明人： Iu-Meng Ho
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/02 , G11C11/405 , G11C11/4125 , G11C2211/4016
摘要： A method of designing an integrated circuit to be Single Event Upset (SEU) immune by converting one or more Single Event Transient (SET) sensitive transistors into at least two serially connected transistors, and spacing the transistors sufficiently far apart so that the probability of a specified high-energy particle striking both transistors at the same time is remote.
摘要翻译：通过将一个或多个单事件瞬态（SET）敏感晶体管转换成至少两个串联连接的晶体管，并且使晶体管间隔足够远的方式将集成电路设计为单事件不便（SEU）免疫的方法，使得指定的高能粒子同时撞击两个晶体管是远程的。

4. 发明申请

US20060083098A1 Electronic memory with binary storage elements 失效
标题翻译：具有二进制存储元件的电子存储器
公开(公告)号：US20060083098A1
公开(公告)日：2006-04-20
申请号：US11292741
申请日：2005-12-02
申请人： Iu-Meng Ho
发明人： Iu-Meng Ho
IPC分类号： G11C8/00
CPC分类号： G11C11/56 , G11C7/1006 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C11/16 , G11C11/22 , G11C11/4094 , G11C11/4097 , G11C11/5607 , G11C11/5621 , G11C11/565 , G11C11/5657 , G11C11/5678 , G11C13/0004 , G11C16/0408 , G11C16/0416 , G11C16/0441 , G11C16/0491 , G11C2211/4013 , G11C2211/5641 , H01L29/785
摘要： An electronic memory using true and complementary dual bit lines and dual binary storage elements cell architecture comprising a memory cell pair with four binary storage elements with each memory cell pair capable of existing in up to sixteen electronic memory states. The four binary storage elements together, normally used to store two true and complementary data bits, are used to store two, three, or four data bits depending on the noise margin allowed and bit width selection. The memory can be ferroelectric memory FeRAM, a flash memory, a ROM, a dynamic memory DRAM, an OUM, a MRAM, a NAND memory, or a NOR memory.
摘要翻译：一种使用真实且互补的双位线和双二进制存储元件的电子存储器单元架构，其包括具有四个二进制存储元件的存储器单元对，每个存储器单元对能够存在多达十六个电子存储器状态。通常用于存储两个真实和互补数据位的四个二进制存储元件一起用于存储两个，三个或四个数据位，这取决于允许的噪声容限和位宽选择。存储器可以是铁电存储器FeRAM，闪速存储器，ROM，动态存储器DRAM，OUM，MRAM，NAND存储器或NOR存储器。

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