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    • 8. 发明授权
    • Solid-state imaging device comprising a holding circuit and driving method thereof
    • 固态成像装置,包括保持电路及其驱动方法
    • US08817143B2
    • 2014-08-26
    • US13271466
    • 2011-10-12
    • Takahiko MurataTakayoshi YamadaYoshihisa KatoShigetaka Kasuga
    • Takahiko MurataTakayoshi YamadaYoshihisa KatoShigetaka Kasuga
    • H04N3/14H04N5/217
    • H04N5/361H01L27/14643H04N5/3742H04N5/3745
    • A plurality of pixel circuits arranged in rows and columns, and each of which outputs an electric signal according to an amount of received light; a first column signal line provided for each of the columns, and for sequentially transferring the electric signals from said pixel circuits in a corresponding column; and a holding circuit provided for each of the pixel circuits in each column, and which holds the electric signal transferred through the column signal line in the corresponding column are provided. A holding circuit includes a first capacitor which holds a first electric signal of the corresponding pixel circuit in a reset state; and a second capacitor which holds a second electric signal after the corresponding pixel circuit receives light. A difference circuit calculates a difference between two electric signals held by the first capacitor and the second capacitor in a same holding circuit.
    • 多个以行和列排列的像素电路,每个像素电路根据接收的光量输出电信号; 为每个列提供的第一列信号线,并且用于从相应列中的所述像素电路顺序传送电信号; 并且提供为每列中的每个像素电路提供并保持通过相应列中的列信号线传送的电信号的保持电路。 保持电路包括:第一电容器,其将相应像素电路的第一电信号保持在复位状态; 以及在相应的像素电路接收光之后保持第二电信号的第二电容器。 差分电路在相同的保持电路中计算由第一电容器和第二电容器保持的两个电信号之间的差。
    • 10. 发明授权
    • Semiconductor memory device and drive method therefor
    • 半导体存储器件及其驱动方法
    • US06707704B2
    • 2004-03-16
    • US10392843
    • 2003-03-21
    • Yoshihisa KatoYasuhiro ShimadaTakayoshi Yamada
    • Yoshihisa KatoYasuhiro ShimadaTakayoshi Yamada
    • G11C1122
    • G11C11/22
    • The semiconductor memory device of the invention includes at least three memory cell blocks arranged in a word line direction. Each of the memory cell blocks includes a plurality of memory cells arranged in a bit line direction. Each of the memory cells includes a ferroelectric capacitor for storing data by displacement of polarization of a ferroelectric film and a selection transistor connected to one of paired electrodes of the ferroelectric capacitor. Each of the memory cell blocks also includes: a bit line, a sub-bit line and a source line extending in the bit line direction; and a read transistor having a gate connected to one end of the sub-bit line, a source connected to the source line, and a drain connected to one end of the bit line. The read transistor reads data by detecting the displacement of the polarization of the ferroelectric film of the ferroelectric capacitor of a data read memory cell from which data is read among the plurality of memory cells. The sub-bit lines of any two of the memory cell blocks are connected to each other via a sub-bit line coupling switch.
    • 本发明的半导体存储器件包括沿字线方向布置的至少三个存储单元块。 每个存储单元块包括以位线方向排列的多个存储单元。 每个存储单元包括用于通过铁电薄膜的极化位移存储数据的铁电电容器和连接到铁电体电容器的一对电极之一的选择晶体管。 每个存储单元块还包括:位线,子位线和沿位线方向延伸的源极线; 以及读取晶体管,其具有连接到子位线的一端的栅极,连接到源极线的源极和连接到位线的一端的漏极。 读取晶体管通过检测在多个存储单元中从其读取数据的数据读取存储单元的铁电电容器的铁电体的极化的位移来读取数据。 任何两个存储单元块的子位线通过子位线耦合开关相互连接。