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31. 发明申请

US20160032447A1 NICKEL-CHROMIUM-SILICON BASED COATINGS 有权
标题翻译：镍基硅基涂料
公开(公告)号：US20160032447A1
公开(公告)日：2016-02-04
申请号：US13847953
申请日：2013-03-20
申请人： Southwest Research Institute
发明人： Kuang-Tsan Kenneth CHIANG
IPC分类号： C23C14/35 , C23C14/06 , C23C14/34
CPC分类号： C23C14/352 , C23C14/165 , C23C14/345 , C23C14/3485 , C23C28/321 , C23C28/34
摘要： A method of depositing Ni—Cr and Si coatings onto a turbine component comprising supplying a Ni—Cr target and Si target with a dual-gun magnetron sputtering system; introducing inert gas and negatively biasing the magnet assembly; grounding or negatively biasing the turbine component to be coated; rotating the turbine component, wherein the turbine component has a surface; and forming a Ni—Cr and Si coating on the component surface.
摘要翻译：一种将Ni-Cr和Si涂层沉积到涡轮部件上的方法，包括用双枪磁控溅射系统提供Ni-Cr靶和Si靶; 引入惰性气体并负极地偏置磁体组件; 对待涂覆的涡轮机部件进行接地或负偏置; 旋转所述涡轮机部件，其中所述涡轮机部件具有表面; 并在组件表面上形成Ni-Cr和Si涂层。

32. 发明申请

US20160032445A1 PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD 审中-公开
标题翻译：等离子体加工设备和等离子体处理方法
公开(公告)号：US20160032445A1
公开(公告)日：2016-02-04
申请号：US14799650
申请日：2015-07-15
申请人： Tokyo Electron Limited
发明人： Yoshihide KIHARA , Masanobu HONDA , Toru HISAMATSU
IPC分类号： C23C14/34 , H01J37/34 , C23C14/06
CPC分类号： C23C14/34 , C23C14/0021 , C23C14/0036 , C23C14/06 , C23C14/0605 , C23C14/0694 , C23C14/3414 , C23C14/3435 , C23C14/345 , C23C16/30 , C23C16/44 , C23C16/448 , C23C16/505 , C23C16/509 , H01J37/32568 , H01J37/32577 , H01J37/3414 , H01J37/3417 , H01J37/3426 , H01J37/3432 , H01J37/3438 , H01J37/3491
摘要： A plasma processing apparatus includes a first electrode, a second electrode disposed to face the first electrode, a chamber, a first high-frequency power supply, a direct-current power supply, and a gas supply source. The plasma processing apparatus generates first plasma to form a film of a reaction product on the second electrode by causing the first high-frequency power supply to supply first high-frequency power to the second electrode and causing the gas supply source to supply a first gas into the chamber; and generates second plasma to sputter the film of the reaction product by causing the first high-frequency power supply to supply the first high-frequency power to the second electrode, causing the direct-current power supply to supply direct-current power to the second electrode, and causing the gas supply source to supply a second gas into the chamber.
摘要翻译：等离子体处理装置包括第一电极，与第一电极相对设置的第二电极，室，第一高频电源，直流电源和气体供给源。等离子体处理装置通过使第一高频电源向第二电极提供第一高频电力并且使气体供给源提供第一气体而产生第一等离子体以在第二电极上形成反应产物的膜进入房间并通过使第一高频电源向第二电极提供第一高频电力而产生第二等离子体以溅射反应产物的膜，从而使直流电源向第二高频电源提供直流电力电极，并且使气体供应源将第二气体供应到室中。

33. 发明授权

US09240378B2 Method of forming a copper layer using physical vapor deposition 有权
标题翻译：使用物理气相沉积法形成铜层的方法
公开(公告)号：US09240378B2
公开(公告)日：2016-01-19
申请号：US14279360
申请日：2014-05-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Ken-Yu Chang , Hung-Wen Su
IPC分类号： H01L21/768 , H01L23/532 , H01L23/528 , H01L21/285
CPC分类号： H01L23/5226 , C23C14/046 , C23C14/165 , C23C14/345 , C23C14/35 , H01L21/2855 , H01L21/76816 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76873 , H01L21/76877 , H01L21/76879 , H01L23/528 , H01L23/5283 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1.
摘要翻译：一种形成半导体结构的方法包括以下步骤：提供衬底; 在衬底上形成电介质; 形成凹陷在所述电介质的顶表面下方的开口; 在所述开口的侧壁上形成阻挡层; 进行物理气相沉积（PVD）以在阻挡层上形成铜层，所述开口的角部以预定的重新溅射比与顶表面和顶表面相交，使得铜层的厚度比阻挡层和顶部表面上的铜层的厚度基本上大于1。

34. 发明申请

US20160002792A1 DECORATIVE, JET-BLACK COATING 有权
标题翻译：装饰，喷漆黑漆
公开(公告)号：US20160002792A1
公开(公告)日：2016-01-07
申请号：US14769449
申请日：2014-02-10
申请人： OERLIKON SURFACE SOLUTIONS AG, TRÜBBACH
发明人： Sebastien Guimond , Manfred Wurzer , Franz Widowitz
IPC分类号： C23C28/04 , C23C16/513 , C23C14/34
CPC分类号： C23C28/048 , C23C14/345 , C23C16/006 , C23C16/0272 , C23C16/26 , C23C16/45523 , C23C16/513 , C23C28/046
摘要： A jet-black coating that resists wear; first, at least one DLC layer with a high degree of hardness is applied to a component and then a gradient layer, whose density decreases in the direction toward the surface, is applied to this DLC layer. By means of the refraction index progression that this produces in the gradient layer, the gradient layer functions as a reflection-reducing layer.
摘要翻译：耐磨损的喷黑涂层; 首先，将具有高硬度的至少一个DLC层施加到部件上，然后将其密度沿着朝向表面的方向减小的梯度层施加到该DLC层。通过在梯度层中产生的折射率进程，梯度层用作反射减少层。

35. 发明申请

US20150357209A1 NEGATIVE ION CONTROL FOR DIELECTRIC ETCH 审中-公开
标题翻译：用于电介质蚀刻的负离子控制
公开(公告)号：US20150357209A1
公开(公告)日：2015-12-10
申请号：US14827052
申请日：2015-08-14
申请人： Lam Research Corporation
发明人： Alexei Marakhtanov , Mirzafer K. Abatchev , Rajinder Dhindsa , Eric Hudson , Andrew D. Bailey, III
IPC分类号： H01L21/67 , H01L21/66 , H01L21/311
CPC分类号： H01L21/67069 , C23C14/345 , C23C16/505 , H01J37/32091 , H01J37/32137 , H01J2237/334 , H01J2237/3343 , H01J2237/3348 , H01L21/3065 , H01L21/31116 , H01L22/20 , H05H2001/4675
摘要： Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer.
摘要翻译：提供了在电容耦合等离子体室中用于半导体处理的装置，方法和计算机程序。腔室包括底部射频（RF）信号发生器，顶部RF信号发生器和RF相位控制器。底部RF信号发生器耦合到室中的底部电极，并且顶部RF信号发生器耦合到顶部电极。此外，底部RF信号被设置在第一相位，并且顶部RF信号被设置在第二阶段。 RF相位控制器可操作以接收底部RF信号并且可操作以设置第二相位的值。此外，RF相位控制器可操作以跟踪第一相位和第二相位，以保持最大RF信号的最大值与底部RF信号的最小值之间的时间差大约为预定的常数值，导致增加到晶片表面的负离子通量。

36. 发明授权

US09051653B2 Rolling bearing 有权
标题翻译：滚动轴承
公开(公告)号：US09051653B2
公开(公告)日：2015-06-09
申请号：US13637953
申请日：2011-03-30
申请人： Hideyuki Tsutsui , Kouya Oohira , Naoko Ito
发明人： Hideyuki Tsutsui , Kouya Oohira , Naoko Ito
IPC分类号： F16C33/32 , C23C28/00 , C23C14/02 , C23C14/06 , C23C14/35 , C23C14/56 , F16C33/42 , F16C33/44 , F16C33/62 , F16C33/30 , C23C14/34
CPC分类号： C23C28/00 , C23C14/024 , C23C14/025 , C23C14/027 , C23C14/0605 , C23C14/345 , C23C14/35 , C23C14/568 , C23C28/322 , C23C28/34 , C23C28/341 , C23C28/343 , C23C28/347 , C23C28/36 , F16C19/06 , F16C33/30 , F16C33/427 , F16C33/445 , F16C33/62 , F16C2206/04
摘要： The present invention provides a rolling bearing in which the peeling resistances of a DLC film formed on raceway of inner and outer rings and a sliding surface of a cage are improved to allow the intrinsic properties of the DLC film to be displayed so that the rolling bearing is excellent in its resistance to seizing, wear, and corrosion. A rolling bearing (1) has an inner ring (2), an outer ring (3), a plurality of rolling elements (4), and a cage (5). A hard film (8) is formed on a curved surface such as a raceway (2a) of the inner ring (2), a raceway (3a) of the outer ring (3), and the like. The hard film (8) is composed of a foundation layer, composed mainly of Cr, which is formed directly on the curved surface.
摘要翻译：本发明提供了一种滚动轴承，其中在内圈和外圈的滚道上形成的DLC膜的抗剥离性和保持架的滑动表面得到改善，使DLC膜的固有特性能够显示，使得滚动轴承具有优异的耐咬住性，耐磨性和耐腐蚀性。滚动轴承（1）具有内圈（2），外圈（3），多个滚动元件（4）和保持架（5）。在内圈（2）的滚道（2a），外圈（3）的滚道（3a）等曲面上形成有硬膜（8）。硬膜（8）由直接形成在曲面上的主要由Cr构成的基础层构成。

37. 发明授权

US08895450B2 Low resistivity tungsten PVD with enhanced ionization and RF power coupling 有权
标题翻译：具有增强电离和RF功率耦合的低电阻率钨PVD
公开(公告)号：US08895450B2
公开(公告)日：2014-11-25
申请号：US14054477
申请日：2013-10-15
申请人： Applied Materials, Inc.
发明人： Yong Cao , Xianmin Tang , Srinivas Gandikota , Wei D. Wang , Zhendong Liu , Kevin Moraes , Muhammad M. Rasheed , Thanh X. Nguyen , Ananthkrishna Jupudi
IPC分类号： H01L21/302 , H01L21/461 , H01L21/28 , C23C14/35 , H01L21/285 , C23C14/34 , H01L29/49 , C23C14/16 , H01L29/78 , H01L29/51
CPC分类号： H01L21/28079 , C23C14/165 , C23C14/345 , C23C14/35 , H01L21/28088 , H01L21/2855 , H01L29/4966 , H01L29/517 , H01L29/78
摘要： Embodiments described herein provide a semiconductor device and methods and apparatuses of forming the same. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal nitride film layer on the conductive film layer, depositing a silicon-containing film layer on the refractory metal nitride film layer, and depositing a tungsten film layer on the silicon-containing film layer.
摘要翻译：本文所述的实施例提供了一种半导体器件及其形成方法和装置。半导体器件包括在源极和漏极区域之间的衬底上具有源极和漏极区域以及栅电极堆叠的衬底。在一个实施例中，该方法包括将衬底定位在处理室内，其中衬底包括源极和漏极区域，源极和漏极区域之间的栅极介电层以及栅极电介质层上的导电膜层。该方法还包括在导电膜层上沉积难熔金属氮化物膜层，在难熔金属氮化物膜层上沉积含硅膜层，并在含硅膜层上沉积钨膜层。

38. 发明授权

US08846451B2 Methods for depositing metal in high aspect ratio features 有权
标题翻译：在高宽比特征中沉积金属的方法
公开(公告)号：US08846451B2
公开(公告)日：2014-09-30
申请号：US13178870
申请日：2011-07-08
申请人： Alan Ritchie , Karl Brown , John Pipitone
发明人： Alan Ritchie , Karl Brown , John Pipitone
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/285 , H01J37/34 , H01L21/768 , C23C14/34 , C23C14/04 , C23C14/35 , C23C16/503 , C23C16/52 , C23C16/56
CPC分类号： H01L21/76898 , C23C14/046 , C23C14/34 , C23C14/345 , C23C14/3492 , C23C14/354 , C23C16/503 , C23C16/52 , C23C16/56 , H01J37/3408 , H01J2237/3327 , H01L21/2855 , H01L21/76865 , H01L21/76873
摘要： Methods for depositing metal in high aspect ratio features formed on a substrate are provided herein. In some embodiments, a method includes applying first RF power at VHF frequency to target comprising metal disposed above substrate to form plasma, applying DC power to target to direct plasma towards target, sputtering metal atoms from target using plasma while maintaining pressure in PVD chamber sufficient to ionize predominant portion of metal atoms, depositing first plurality of metal atoms on bottom surface of opening and on first surface of substrate, applying second RF power to redistribute at least some of first plurality from bottom surface to lower portion of sidewalls of the opening, and depositing second plurality of metal atoms on upper portion of sidewalls by reducing amount of ionized metal atoms in PVD chamber, wherein first and second pluralities form a first layer deposited on substantially all surfaces of opening.
摘要翻译：本文提供了在基板上形成的高纵横比特征中沉积金属的方法。在一些实施例中，一种方法包括将VHF频率的第一RF功率应用于设置在衬底上方的金属以形成等离子体，施加直流电力以将等离子体引向目标，使用等离子体从靶中溅射金属原子，同时保持PVD室中的压力足够以电离金属原子的主要部分，在开口的底表面和衬底的第一表面上沉积第一多个金属原子，施加第二RF功率以重新分配从开口的侧壁的底表面到下部的至少一些，以及通过减少PVD室中的电离金属原子的量将第二多个金属原子沉积在侧壁的上部，其中第一和第二多个形成沉积在开口的基本上所有表面上的第一层。

39. 发明申请

US20140287163A1 METHOD OF FORMING COPPER WIRING AND METHOD AND SYSTEM FOR FORMING COPPER FILM 审中-公开
标题翻译：形成铜线的方法和形成铜膜的方法和系统
公开(公告)号：US20140287163A1
公开(公告)日：2014-09-25
申请号：US14297726
申请日：2014-06-06
申请人： TOKYO ELECTRON LIMITED
发明人： Tadahiro ISHIZAKA , Atsushi GOMI , Takara FUKUSHIMA , Osamu YOKOYAMA , Takashi SAKUMA , Chiaki YASUMURO , Hiroyuki TOSHIMA , Tatsuo HATANO , Yasushi MIZUSAWA , Masamichi HARA , Kenzi SUZUKI
IPC分类号： H01L21/02
CPC分类号： H01L21/02104 , C23C14/025 , C23C14/046 , C23C14/345 , C23C14/541 , C23C14/5806 , C23C16/16 , H01J37/32899 , H01J37/34
摘要： A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding Cu in the trench or hole by forming a Cu film on the Ru film using PVD while annealing the substrate such that migration of copper into the trench or hole occurs.
摘要翻译：提供了一种在衬底中形成的沟槽或孔中形成Cu布线的方法。该方法包括在沟槽或孔的表面上形成阻挡膜，在阻挡膜上形成Ru膜，并且通过在使衬底退火的同时在PVD膜上形成Cu膜而将Cu嵌入沟槽或孔中，使得发生铜进入沟槽或孔的迁移。

40. 发明申请

US20140216922A1 RF DELIVERY SYSTEM WITH DUAL MATCHING NETWORKS WITH CAPACITIVE TUNING AND POWER SWITCHING 审中-公开
标题翻译：具有电力调谐和电源开关的双重匹配网络的射频输送系统
公开(公告)号：US20140216922A1
公开(公告)日：2014-08-07
申请号：US13761253
申请日：2013-02-07
申请人： APPLIED MATERIALS, INC.
发明人： ALAN A. RITCHIE
IPC分类号： C23C14/34
CPC分类号： C23C14/345 , C23C14/046 , C23C14/35 , C23C14/351 , C23C14/54 , H01J37/32706 , H01J37/3405 , H01J37/3444
摘要： Apparatus and method for delivering power to a substrate processing chamber may include a target and a substrate support pedestal disposed in the chamber, a pedestal impedance match device coupled between the substrate support pedestal and ground, wherein the pedestal impedance match device is configured to adjust a bias voltage on the substrate support pedestal, a target impedance match device coupled between the target and ground, wherein the target impedance match device is configured to adjust a bias voltage on the target, a switch electrically coupled to the pedestal impedance match device and the target impedance match device, a first RF power source coupled to the switch, wherein the switch is configured to direct high frequency voltage from the first RF power source to either the target or the substrate support pedestal, and a second RF power source coupled to the substrate support pedestal.
摘要翻译：用于向基板处理室输送功率的装置和方法可以包括设置在腔室中的靶和基板支撑台座，耦合在基板支撑基座和地之间的基座阻抗匹配装置，其中基座阻抗匹配装置被配置成调整耦合在目标和地之间的目标阻抗匹配装置，其中所述目标阻抗匹配装置被配置成调整所述目标上的偏置电压，电耦合到所述基座阻抗匹配装置和所述目标的开关阻抗匹配装置，耦合到所述开关的第一RF电源，其中所述开关被配置为将来自所述第一RF电源的高频电压引导到所述靶或所述衬底支撑基座，以及耦合到所述衬底的第二RF电源支撑底座。

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