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31. 发明申请

US20090250818A1 VIA ELECTROMIGRATION IMPROVEMENT BY CHANGING THE VIA BOTTOM GEOMETRIC PROFILE 有权
标题翻译：通过改变通过底部几何轮廓的电力改进
公开(公告)号：US20090250818A1
公开(公告)日：2009-10-08
申请号：US12486521
申请日：2009-06-17
申请人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L23/522
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
摘要翻译：描述了一种用于提高半导体器件中的电迁移阻力的集成方法。在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

32. 发明申请

US20090250764A1 STRESSED DIELECTRIC LAYER WITH STABLE STRESS 有权
标题翻译：具有稳定应力的应力介电层
公开(公告)号：US20090250764A1
公开(公告)日：2009-10-08
申请号：US12062535
申请日：2008-04-04
申请人： Huang LIU , Jeff SHU , Luona GOH , Wei LU
发明人： Huang LIU , Jeff SHU , Luona GOH , Wei LU
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/78 , H01L21/76224 , H01L29/665 , H01L29/7843
摘要： An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O3 TEOS oxide having a stress retaining dopant. The O3 TEOS oxide induces a stress in a channel region of the transistor.
摘要翻译：提供了一种集成电路，其具有衬底和在衬底的有源区域中的晶体管。衬底还具有具有电介质材料的隔离区域。在一个实施例中，预先金属介电层设置在衬底和晶体管的上方。隔离区域或预金属介电层中的至少一个包括具有应力保持掺杂剂的O 3 TEOS氧化物。 O 3 TEOS氧化物在晶体管的沟道区域中引起应力。

33. 发明授权

US07585746B2 Process integration scheme of SONOS technology 有权
标题翻译： SONOS技术的过程集成方案
公开(公告)号：US07585746B2
公开(公告)日：2009-09-08
申请号：US11485949
申请日：2006-07-12
申请人： Sung Mun Jung , Yoke Leng Louis Lim , Sripad Nagarad , Dong Kyun Sohn , Dong Hua Liu , Xiao Yu Chen , Rachel Low
发明人： Sung Mun Jung , Yoke Leng Louis Lim , Sripad Nagarad , Dong Kyun Sohn , Dong Hua Liu , Xiao Yu Chen , Rachel Low
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11568
摘要： In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.
摘要翻译：在非限制性实例中，我们提供具有细胞区域和非细胞区域的底物。我们在衬底上形成隧道介电层，电荷存储层，顶部绝缘层（例如ONO）。然后我们在顶部绝缘层上形成导电焊盘层。我们在焊盘层，电荷存储层和隧道电介质层中形成隔离沟槽并进入衬底。我们在隔离沟中形成隔离区。我们去除非单元区域中的焊盘层，电荷存储层和隧道介电层。我们在衬垫层和衬底表面上形成栅极层。我们完成以形成单元区域中的存储器（例如SONOS）器件和衬底的非单元区域中的其他器件。

34. 发明授权

US07573099B2 Semiconductor device layout and channeling implant process 有权
标题翻译：半导体器件布局和沟道植入过程
公开(公告)号：US07573099B2
公开(公告)日：2009-08-11
申请号：US11170576
申请日：2005-06-28
申请人： Yisuo Li , Xiaohong Jiang , Francis Benistant
发明人： Yisuo Li , Xiaohong Jiang , Francis Benistant
IPC分类号： H01L29/48 , H01L27/088
CPC分类号： H01L29/66659 , H01L21/26586 , H01L29/045
摘要： A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction ) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.
摘要翻译：一种使用植入过程形成分级结的装置结构和方法。本发明的实施例包括将离子注入到所述硅衬底中以形成与所述栅极相邻的掺杂区域。 Si晶体结构中的沟道区域（沟道方向<100>）与大角度倾斜和扭曲注入工艺相结合的方向产生具有更梯度结的掺杂区域。取向和植入过程产生更多的离子通道。离子的通道产生更分级的结。当在HV MOS TX上实现时，LDD的分级结增加了击穿电压。另一实施例是具有环形通道区域的FET。

35. 发明申请

US20090167466A1 TUNABLE HIGH QUALITY FACTOR INDUCTOR 有权
标题翻译：可靠的高品质因子电感
公开(公告)号：US20090167466A1
公开(公告)日：2009-07-02
申请号：US11967270
申请日：2007-12-31
申请人： Ping QIU , Chirn Chye BOON , Johnny Kok Wai CHEW , Kiat Seng YEO , Manh Anh DO , Lap CHAN , Suh Fei LIM
发明人： Ping QIU , Chirn Chye BOON , Johnny Kok Wai CHEW , Kiat Seng YEO , Manh Anh DO , Lap CHAN , Suh Fei LIM
IPC分类号： H03J3/00 , H01F27/06
CPC分类号： H03J3/20 , H01F17/0006 , H01F2017/0073 , H03H11/48
摘要： An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.
摘要翻译：具有高质量（Q）因子的电感器电路包括初级电感器和补偿子电路。补偿子电路与主电感器电隔离。补偿子电路与初级电感器磁耦合，以补偿初级电感器的损耗。

36. 发明授权

US07528445B2 Wing gate transistor for integrated circuits 有权
标题翻译：用于集成电路的翼栅晶体管
公开(公告)号：US07528445B2
公开(公告)日：2009-05-05
申请号：US11380378
申请日：2006-04-26
申请人： Timothy Phua , Kheng Chok Tee , Liang Choo Hsia
发明人： Timothy Phua , Kheng Chok Tee , Liang Choo Hsia
IPC分类号： H01L29/76 , H01L31/113 , H01L21/338
CPC分类号： H01L29/6653 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.
摘要翻译：提供一种用于形成半导体器件的系统。在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。盖材料和栅极材料的一部分被加工以形成盖和门体部分。门体部分上的翼部由栅极材料的剩余部分形成。栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

37. 发明授权

US07524755B2 Entire encapsulation of Cu interconnects using self-aligned CuSiN film 有权
标题翻译：使用自对准CuSiN膜的Cu互连的全封装
公开(公告)号：US07524755B2
公开(公告)日：2009-04-28
申请号：US11358934
申请日：2006-02-22
申请人： Johnny Widodo , Bei Chao Zhang , Tong Qing Chen , Yong Kong Siew , Fan Zhang , San Leong Liew , John Sudijono , Liang Choo Hsia
发明人： Johnny Widodo , Bei Chao Zhang , Tong Qing Chen , Yong Kong Siew , Fan Zhang , San Leong Liew , John Sudijono , Liang Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L24/03 , H01L24/05 , H01L2224/05073 , H01L2224/05546 , H01L2224/05647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/14 , H01L2924/01039 , H01L2924/00
摘要： A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.
摘要翻译：形成用于互连的CuSiN构成的阻挡层和盖的方法。我们在半导体结构上的电介质层中提供互连开口。通过与第一铜层反应，在互连开口的侧壁和底部上形成CuSiN阻挡层。然后，我们在填充互连开口的CuSiN层上形成互连。我们可以在互连的顶部表面上形成CuSiN覆盖层。

38. 发明申请

US20090081840A1 Method of Forming Field Effect Transistors Using Diluted Hydrofluoric Acid to Remove Sacrificial Nitride Spacers 有权
标题翻译：使用稀释的氢氟酸形成场效应晶体管去除牺牲氮化物间隔物的方法
公开(公告)号：US20090081840A1
公开(公告)日：2009-03-26
申请号：US11858535
申请日：2007-09-20
申请人： Sang-jine Park , Richard O. Henry , Yong Siang Tan , O Sung Kwun , Oh-Jung Kwon
发明人： Sang-jine Park , Richard O. Henry , Yong Siang Tan , O Sung Kwun , Oh-Jung Kwon
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/31111 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/7843
摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, sacrificial nitride spacers on opposing sidewalls of the gate electrode and source/drain regions, which are self-aligned to the sacrificial nitride spacers, on a semiconductor substrate. The sacrificial nitride spacers are selectively removed using a diluted hydrofluoric acid solution having a nitride-to-oxide etching selectivity in excess of one. In order to increase charge carrier mobility within a channel of the field effect transistor, a stress-inducing electrically insulating layer is formed on opposing sidewalls of the gate electrode. This insulating layer is configured to induce a net tensile stress (NMOS) or compressive stress (PMOS) in the channel.
摘要翻译：形成集成电路器件的方法包括在半导体衬底上形成具有栅电极的场效应晶体管，在栅电极的相对侧壁上的牺牲氮化物间隔物和与牺牲氮化物间隔物自对准的源/漏区。使用具有氮化物至氧化物蚀刻选择性的稀释氢氟酸溶液选择性地除去牺牲氮化物间隔物。为了增加场效应晶体管的沟道内的电荷载流子迁移率，在栅电极的相对侧壁上形成应力感应电绝缘层。该绝缘层被配置为在通道中引起净拉伸应力（NMOS）或压缩应力（PMOS）。

39. 发明授权

US07501683B2 Integrated circuit with protected implantation profiles and method for the formation thereof 有权
标题翻译：具有保护注入轮廓的集成电路及其形成方法
公开(公告)号：US07501683B2
公开(公告)日：2009-03-10
申请号：US11421047
申请日：2006-05-30
申请人： Tommy Lai , Pradeep Ramachandramurthy Yelehanka , Jia Zhen Zheng , Weining Li
发明人： Tommy Lai , Pradeep Ramachandramurthy Yelehanka , Jia Zhen Zheng , Weining Li
IPC分类号： H01L29/792
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/31155 , H01L21/3144 , H01L27/1052 , H01L27/11546
摘要： An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.
摘要翻译：集成电路结构包括提供半导体衬底并在半导体衬底上形成至少一个氧化物 - 氮化物 - 氧化物电介质层。在形成氧化物 - 氮化物 - 氧化物电介质层之后，至少一个注入形成在氧化物 - 氮化物 - 氧化物介电层下方的半导体衬底的至少一个区域中。

40. 发明申请

US20090014807A1 DUAL STRESS LINERS FOR INTEGRATED CIRCUITS 审中-公开
标题翻译：用于集成电路的双应力线
公开(公告)号：US20090014807A1
公开(公告)日：2009-01-15
申请号：US11777290
申请日：2007-07-13
申请人： Teck Jung TANG , Dae Kwon Kang , Sunfei Fang , Tae Hoon Lee , Scott D. Allen , Fang Chen , Frank Huebinger , Jun Jung Kim , Jae Eun Park
发明人： Teck Jung TANG , Dae Kwon Kang , Sunfei Fang , Tae Hoon Lee , Scott D. Allen , Fang Chen , Frank Huebinger , Jun Jung Kim , Jae Eun Park
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823871 , H01L21/823878 , H01L29/665 , H01L29/7843
摘要： Dual stress liners for CMOS applications are provided. The dual stress liners can be formed from silicon nitride having a first portion for inducing a first stress and a second portion for inducing a second stress. An interface between the first and second stress portions is self-aligned and co-planar. To produce a co-planar self-aligned interface, polishing, for example, mechanical chemical polishing is used.
摘要翻译：提供用于CMOS应用的双重应力衬垫。双重应力衬垫可以由具有用于诱发第一应力的第一部分的氮化硅和用于引起第二应力的第二部分形成。第一和第二应力部分之间的界面是自对准的并且是共面的。为了产生共面自对准界面，使用例如机械化学抛光进行抛光。

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