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1. 发明授权

US08992691B2 Partial solution replacement in recyclable persulfuric acid cleaning systems 有权
标题翻译：可再循环过硫酸清洗系统部分溶液更换
公开(公告)号：US08992691B2
公开(公告)日：2015-03-31
申请号：US13080097
申请日：2011-04-05
申请人： Richard O. Henry , David F. Hilscher , Sandi E. Merritt , Charles J. Taft , Robert W. Zigner, Jr.
发明人： Richard O. Henry , David F. Hilscher , Sandi E. Merritt , Charles J. Taft , Robert W. Zigner, Jr.
IPC分类号： H01L21/67 , H01L21/02
CPC分类号： H01L21/67057 , G01N27/4161 , H01L21/02052 , H01L21/67017
摘要： A method of implementing cleaning solution replacement in a recyclable fluid cleaning system for semiconductor wafers includes activating electrode current for an electrolysis reactor included in the cleaning system. At least one of electrode voltage and operating time for the electrolysis reactor is monitored, until a trigger point has been reached. The trigger point includes one of the electrode voltage reaching a predetermined threshold voltage value, a process time counter reaching a predetermined counter value, and a time value that the electrode voltage has been at the threshold voltage value reaching predetermined value. The process time counter is incremented based on one or more of actual wafer processing time, wafer type, number of wafers processed, and thickness of material to be stripped. Upon reaching the trigger point, the electrode current is deactivated, and at least a portion of cleaning system fluid is drained and replaced with fresh cleaning fluid.
摘要翻译：在用于半导体晶片的可再循环流体清洁系统中实施清洁溶液置换的方法包括激活包括在清洁系统中的电解反应器的电极电流。监控电解反应器的电极电压和操作时间中的至少一个，直到达到触发点。触发点包括达到预定阈值电压值的电极电压中的一个，达到预定计数器值的处理时间计数器和电极电压已经达到阈值电压值的时间值达到预定值。基于实际晶片处理时间，晶片类型，处理的晶片数量和要剥离的材料的厚度中的一个或多个，处理时间计数器增加。在达到触发点时，电极电流被去激活，清洁系统流体的至少一部分被排出并用新鲜的清洁流体代替。

2. 发明授权

US07902082B2 Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers 有权
标题翻译：使用稀释的氢氟酸来形成场效应晶体管以去除牺牲性氮化物间隔物的方法
公开(公告)号：US07902082B2
公开(公告)日：2011-03-08
申请号：US11858535
申请日：2007-09-20
申请人： Sang Jine Park , Richard O. Henry , Yong Siang Tan , O Sung Kwon , Oh Jung Kwon
发明人： Sang Jine Park , Richard O. Henry , Yong Siang Tan , O Sung Kwon , Oh Jung Kwon
IPC分类号： H01L21/302
CPC分类号： H01L29/66636 , H01L21/31111 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/7843
摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, sacrificial nitride spacers on opposing sidewalls of the gate electrode and source/drain regions, which are self-aligned to the sacrificial nitride spacers, on a semiconductor substrate. The sacrificial nitride spacers are selectively removed using a diluted hydrofluoric acid solution having a nitride-to-oxide etching selectivity in excess of one. In order to increase charge carrier mobility within a channel of the field effect transistor, a stress-inducing electrically insulating layer is formed on opposing sidewalls of the gate electrode. This insulating layer is configured to induce a net tensile stress (NMOS) or compressive stress (PMOS) in the channel.
摘要翻译：形成集成电路器件的方法包括在半导体衬底上形成具有栅电极的场效应晶体管，在栅电极的相对侧壁上的牺牲氮化物间隔物和与牺牲氮化物间隔物自对准的源/漏区。使用具有氮化物至氧化物蚀刻选择性的稀释氢氟酸溶液选择性地除去牺牲氮化物间隔物。为了增加场效应晶体管的沟道内的电荷载流子迁移率，在栅电极的相对侧壁上形成应力感应电绝缘层。该绝缘层被配置为在通道中引起净拉伸应力（NMOS）或压缩应力（PMOS）。

3. 发明申请

US20100009502A1 Semiconductor Fabrication Process Including An SiGe Rework Method 有权
标题翻译：包括SiGe返工方法的半导体制造工艺
公开(公告)号：US20100009502A1
公开(公告)日：2010-01-14
申请号：US12172756
申请日：2008-07-14
申请人： Yong Siang Tan , Chung Woh Lai , Jin-Ping Han , Henry K. Utomo , Judson R. Holt , Eric Harley , Richard O. Henry , Richard J. Murphy
发明人： Yong Siang Tan , Chung Woh Lai , Jin-Ping Han , Henry K. Utomo , Judson R. Holt , Eric Harley , Richard O. Henry , Richard J. Murphy
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/30608 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.
摘要翻译：一种制造半导体器件的方法包括形成SiGe区域。 SiGe区可以是嵌入式源极和漏极区域，或者是半导体器件内的压缩SiGe沟道层或其它SiGe区域。将SiGe区域暴露于SC1溶液，并且选择性地除去SiGe区域的多余表面部分。 SC1蚀刻工艺可以是返工方法的一部分，其中通过暴露SiGe和保持在升高的温度下的SC1溶液来选择性地除去SiGe的过度生长区域。进行蚀刻处理足以除去SiGe的多余表面部分的一段时间。 SC1蚀刻工艺可以在约25℃至约65℃的升高的温度下进行。

4. 发明授权

US07253106B2 Manufacturable CoWP metal cap process for copper interconnects 有权
标题翻译：用于铜互连的可制造的CoWP金属帽工艺
公开(公告)号：US07253106B2
公开(公告)日：2007-08-07
申请号：US10905230
申请日：2004-12-22
申请人： Darryl D. Restaino , Donald F. Canaperi , Judith M. Rubino , Sean P. E. Smith , Richard O. Henry , James E. Fluegel , Mahadevaiyer Krishnan
发明人： Darryl D. Restaino , Donald F. Canaperi , Judith M. Rubino , Sean P. E. Smith , Richard O. Henry , James E. Fluegel , Mahadevaiyer Krishnan
IPC分类号： H01L21/44
CPC分类号： H01L21/288 , C23C18/1241 , C23C18/1607 , C23C18/1608 , C23C18/1844 , C23C18/50 , H01L21/76849 , H01L21/76874 , H05K3/244 , H05K2203/0716 , H05K2203/072
摘要： A method to electrolessly plate a CoWP alloy on copper in a reproducible manner that is effective for a manufacturable process. In the method, a seed layer of palladium (Pd) is deposited on the copper by an aqueous seeding solution of palladium acetate, acetic acid and chloride. Thereafter, a complexing solution is applied to remove any Pd ions which are adsorbed on surfaces other than the copper. Finally, a plating solution of cobalt (Co), tungsten (W) and phosphorous (P) is applied to the copper so as to deposit a layer of CoWP on the Pd seed and copper.
摘要翻译：一种以可再生的方式对铜上的CoWP合金进行无电镀的方法，该方法对于可制造的工艺是有效的。在该方法中，通过乙酸钯，乙酸和氯化物的水性接种溶液将铜（Pd）种子层沉积在铜上。此后，应用络合溶液以除去吸附在除铜之外的表面上的任何Pd离子。最后，将铜（Co），钨（W）和磷（P）的电镀溶液施加到铜上，以便在Pd种子和铜上沉积CoWP层。

5. 发明授权

US08337627B2 Cleaning exhaust screens in a manufacturing process 有权
标题翻译：在制造过程中清洁排气筛
公开(公告)号：US08337627B2
公开(公告)日：2012-12-25
申请号：US12571477
申请日：2009-10-01
申请人： John A. Fitzsimmons , Richard O. Henry
发明人： John A. Fitzsimmons , Richard O. Henry
IPC分类号： B08B3/08 , B01D41/04 , B01D29/66
CPC分类号： B08B3/08 , B01D41/04
摘要： A method of cleaning an screen in a manufacturing process step that employs a chamber including a drain line having a screen configured and disposed in the chamber above the drain line to trap soluble materials includes detecting a build-up of soluble material on the screen, ceasing a work operation in the chamber, and initiating a screen cleaning operation. The screen cleaning operation includes closing a computer operated valve fluidly connected to the drain line to fluidly isolate a portion of the chamber, automatically introducing an amount of solvent into the chamber once the computer operated valve is closed with the amount of solvent filling the chamber and/or the drain line to fully immerse the screen, and opening the operated valve after a predetermined amount of time to empty the chamber and the drain line of solvent once the soluble materials trapped on the screen are dissolved.
摘要翻译：一种在制造工艺步骤中清洁屏幕的方法，该方法采用包括排水线的室，该室具有配置并设置在排出管线上方的室内的筛网以捕获可溶性材料，包括检测可溶物质在筛网上的积聚，停止在室中进行工作操作，并启动屏幕清洁操作。屏幕清洁操作包括关闭流体地连接到排水管线的计算机操作的阀，以流体地隔离室的一部分，一旦计算机操作的阀被填充室的溶剂量封闭，则自动将一定量的溶剂引入室中， /或排水管线，以完全浸没屏幕，并且一旦被捕获在屏幕上的可溶性材料溶解，则在预定量的时间之后打开操作的阀以清空溶剂和溶剂的排出管线。

6. 发明授权

US07563670B2 Method for etching single-crystal semiconductor selective to amorphous/polycrystalline semiconductor and structure formed by same 有权
标题翻译：用于蚀刻对非晶/多晶半导体有选择性的单晶半导体及其结构的方法
公开(公告)号：US07563670B2
公开(公告)日：2009-07-21
申请号：US11558974
申请日：2006-11-13
申请人： Kangguo Cheng , Richard O. Henry , Kenneth T. Settlemyer, Jr.
发明人： Kangguo Cheng , Richard O. Henry , Kenneth T. Settlemyer, Jr.
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/20
CPC分类号： H01L21/32134 , H01L21/30608 , H01L27/10841 , H01L27/10864
摘要： A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.
摘要翻译：一种形成垂直DRAM装置的方法。下沟槽填充有用于电容器的多晶或非晶半导体。上沟槽部分具有暴露的单晶半导体的侧壁。该方法然后包括蚀刻单晶半导体侧壁以将上部沟槽部分加宽超过电容器的半导体填充物的暴露的上表面，以在邻近暴露的上部沟槽的上部沟槽的底部上形成单晶半导体的暴露区域半导体填料的上表面。沟槽顶部绝缘层沉积在上沟槽的底部上方，半导体填充物的上表面和相邻的单晶半导体区域之上。该方法然后包括形成垂直栅极电介质层，其中沟槽顶部绝缘层延伸到垂直栅极绝缘层下方。

7. 发明授权

US07407605B2 Manufacturable CoWP metal cap process for copper interconnects 有权
标题翻译：用于铜互连的可制造的CoWP金属帽工艺
公开(公告)号：US07407605B2
公开(公告)日：2008-08-05
申请号：US11751788
申请日：2007-05-22
申请人： Darryl D. Restaino , Donald F. Canaperi , Judith M. Rubino , Sean P. E. Smith , Richard O. Henry , James E. Fluegel , Mahadevaiyer Krishnan
发明人： Darryl D. Restaino , Donald F. Canaperi , Judith M. Rubino , Sean P. E. Smith , Richard O. Henry , James E. Fluegel , Mahadevaiyer Krishnan
IPC分类号： H01B1/00
CPC分类号： H01L21/288 , C23C18/1241 , C23C18/1607 , C23C18/1608 , C23C18/1844 , C23C18/50 , H01L21/76849 , H01L21/76874 , H05K3/244 , H05K2203/0716 , H05K2203/072
摘要： An aqueous seeding solution of palladium acetate, acetic acid and chloride.
摘要翻译：乙酸钯，乙酸和氯化钠的水溶液接种溶液。

8. 发明申请

US20120255577A1 PARTIAL SOLUTION REPLACEMENT IN RECYCLABLE PERSULFURIC ACID CLEANING SYSTEMS 有权
标题翻译：可循环使用的清洁系统中的部分溶液替代物
公开(公告)号：US20120255577A1
公开(公告)日：2012-10-11
申请号：US13080097
申请日：2011-04-05
申请人： Richard O. Henry , David F. Hilscher , Sandi E. Merritt , Charles J. Taft , Robert W. Zigner, JR.
发明人： Richard O. Henry , David F. Hilscher , Sandi E. Merritt , Charles J. Taft , Robert W. Zigner, JR.
IPC分类号： C23G1/36 , B08B3/10
CPC分类号： H01L21/67057 , G01N27/4161 , H01L21/02052 , H01L21/67017
摘要： A method of implementing cleaning solution replacement in a recyclable fluid cleaning system for semiconductor wafers includes activating electrode current for an electrolysis reactor included in the cleaning system. At least one of electrode voltage and operating time for the electrolysis reactor is monitored, until a trigger point has been reached. The trigger point includes one of the electrode voltage reaching a predetermined threshold voltage value, a process time counter reaching a predetermined counter value, and a time value that the electrode voltage has been at the threshold voltage value reaching predetermined value. The process time counter is incremented based on one or more of actual wafer processing time, wafer type, number of wafers processed, and thickness of material to be stripped. Upon reaching the trigger point, the electrode current is deactivated, and at least a portion of cleaning system fluid is drained and replaced with fresh cleaning fluid.
摘要翻译：在用于半导体晶片的可再循环流体清洁系统中实施清洁溶液置换的方法包括激活包括在清洁系统中的电解反应器的电极电流。监控电解反应器的电极电压和操作时间中的至少一个，直到达到触发点。触发点包括达到预定阈值电压值的电极电压中的一个，达到预定计数器值的处理时间计数器和电极电压已经达到阈值电压值的时间值达到预定值。基于实际晶片处理时间，晶片类型，处理的晶片数量和要剥离的材料的厚度中的一个或多个，处理时间计数器增加。在达到触发点时，电极电流被去激活，清洁系统流体的至少一部分被排出并用新鲜的清洁流体代替。

9. 发明授权

US08021945B2 Bottle-shaped trench capacitor with enhanced capacitance 有权
标题翻译：具有增强电容的瓶形沟槽电容器
公开(公告)号：US08021945B2
公开(公告)日：2011-09-20
申请号：US12423242
申请日：2009-04-14
申请人： Xi Li , Russell H. Arndt , Kangguo Cheng , Richard O. Henry , Jinghong H. Li
发明人： Xi Li , Russell H. Arndt , Kangguo Cheng , Richard O. Henry , Jinghong H. Li
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087 , H01L28/82 , Y10S438/964
摘要： In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.
摘要翻译：根据本发明的一个方面，提供一种用于制造包括沟槽电容器的半导体芯片的方法。在这种方法中，可以通过电介质层中的开口在垂直方向上蚀刻单晶半导体区域，以形成露出单晶半导体材料的粗糙表面的沟槽。沟槽在垂直于垂直方向的第一方向上具有初始侧向尺寸。然后在晶体表面上暴露的半导体材料以结晶方向依赖的方式进行蚀刻，以在沟槽表面暴露半导体材料的多个晶面。然后可以沉积含掺杂剂的衬里以对沟槽的表面进行排列，然后升高衬底的温度以将掺杂剂从含掺杂剂的衬里驱动到与表面相邻的半导体区域中。在这样的步骤中，通常暴露在壁处的半导体材料的一部分被氧化。去除至少一些氧化部分以露出扩大的沟槽的壁，沿着该壁形成介电层和导电材料以形成沟槽电容器。

10. 发明授权

US07955936B2 Semiconductor fabrication process including an SiGe rework method 有权
标题翻译：半导体制造工艺包括SiGe返工方法
公开(公告)号：US07955936B2
公开(公告)日：2011-06-07
申请号：US12172756
申请日：2008-07-14
申请人： Yong Siang Tan , Chung Woh Lai , Jin-Ping Han , Henry K. Utomo , Judson R. Holt , Eric Harley , Richard O. Henry , Richard J. Murphy
发明人： Yong Siang Tan , Chung Woh Lai , Jin-Ping Han , Henry K. Utomo , Judson R. Holt , Eric Harley , Richard O. Henry , Richard J. Murphy
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/30608 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.
摘要翻译：一种制造半导体器件的方法包括形成SiGe区域。 SiGe区可以是嵌入式源极和漏极区域，或者是半导体器件内的压缩SiGe沟道层或其它SiGe区域。将SiGe区域暴露于SC1溶液，并且选择性地除去SiGe区域的多余表面部分。 SC1蚀刻工艺可以是返工方法的一部分，其中通过暴露SiGe和保持在升高的温度下的SC1溶液来选择性地除去SiGe的过度生长区域。进行蚀刻处理足以除去SiGe的多余表面部分的一段时间。 SC1蚀刻工艺可以在约25℃至约65℃的升高的温度下进行。

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