专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090250818A1 VIA ELECTROMIGRATION IMPROVEMENT BY CHANGING THE VIA BOTTOM GEOMETRIC PROFILE 有权
标题翻译：通过改变通过底部几何轮廓的电力改进
公开(公告)号：US20090250818A1
公开(公告)日：2009-10-08
申请号：US12486521
申请日：2009-06-17
申请人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L23/522
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
摘要翻译：描述了一种用于提高半导体器件中的电迁移阻力的集成方法。在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

2. 发明授权

US07781895B2 Via electromigration improvement by changing the via bottom geometric profile 有权
公开(公告)号：US07781895B2
公开(公告)日：2010-08-24
申请号：US12486521
申请日：2009-06-17
申请人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

3. 发明授权

US07691739B2 Via electromigration improvement by changing the via bottom geometric profile 有权
标题翻译：通过改变通孔底部几何轮廓来改善电迁移
公开(公告)号：US07691739B2
公开(公告)日：2010-04-06
申请号：US11374848
申请日：2006-03-13
申请人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
摘要翻译：描述了一种用于提高半导体器件中的电迁移阻力的集成方法。在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

4. 发明授权

US07045455B2 Via electromigration improvement by changing the via bottom geometric profile 有权
标题翻译：通过改变通孔底部几何轮廓来改善电迁移
公开(公告)号：US07045455B2
公开(公告)日：2006-05-16
申请号：US10692028
申请日：2003-10-23
申请人： Beichao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Beichao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
摘要翻译：描述了一种用于提高半导体器件中的电迁移阻力的集成方法。在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

5. 发明授权

US06765296B2 Via-sea layout integrated circuits 有权
标题翻译： Via-sea布局集成电路
公开(公告)号：US06765296B2
公开(公告)日：2004-07-20
申请号：US10044344
申请日：2002-01-10
申请人： Jae Soo Park , Chivukula Subramanyam , Thow Phock Chua , Hong Lim Lee
发明人： Jae Soo Park , Chivukula Subramanyam , Thow Phock Chua , Hong Lim Lee
IPC分类号： H01L2348
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit interconnect is provided having a dielectric layer disposed between a wide top metal line and a wide bottom metal line. A via-sea in the dielectric layer connects the wide top and wide bottom metal lines by means of a first via having a width, a second via having a width and spaced more than two widths away and less than four widths away from the first via.
摘要翻译：提供集成电路互连，其具有设置在宽顶金属线和宽底金属线之间的介电层。电介质层中的通孔通过具有宽度的第一通孔连接宽顶和宽底金属线，第二通孔具有远离第一通孔的宽度和间隔多于两个宽度且小于四个宽度的第二通孔。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式