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31. 发明授权

US5604417A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5604417A
公开(公告)日：1997-02-18
申请号：US992448
申请日：1992-12-17
申请人： Yasuo Kaminaga , Yoji Nishio , Akihiro Tamba , Yutaka Kobayashi , Masataka Minami
发明人： Yasuo Kaminaga , Yoji Nishio , Akihiro Tamba , Yutaka Kobayashi , Masataka Minami
IPC分类号： H01L27/06 , H03K19/013 , H03R19/013
CPC分类号： H01L27/0623 , H03K19/0136
摘要： The device has, on a single substrate, plural internal circuits, plural input circuits for receiving external input signals and outputting the same to the internal circuit, and plural output circuits for receiving signals outputted from the internal circuits and externally outputting the same, in which at least one of the circuits includes a totem-pole output stage of a first NPN bipolar transistor, on the power supply terminal side, and a second NPN bipolar transistor, on the ground side; a first differentiator circuit for providing pulsing action to the base of the first NPN transistor; a pair of series-connected PMOS transistors for controllably driving the second NPN transistor; and feedback MOS transistors for quickening turn-off of the output stage transistors. The circuit can be effected with a second differentiator circuit in place of the series-connected pair of PMOS transistors. Arrangements of circuits can also be effected in which the totem-pole connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side. With such circuit configurations, the output signal swing is maximized, and the differentiator circuit provides for temporary saturation along with a quickened recovery therefrom, thereby reducing transmission delay time and achieving low power consumption. The device can be implemented by circuitry which employs the bootstrap effect as well as IIL (I.sup.2 L) design schemes.
摘要翻译：该装置在单个基板上具有多个内部电路，用于接收外部输入信号并将其输出到内部电路的多个输入电路，以及用于接收从内部电路输出并从外部输出信号的多个输出电路，其中至少一个电路包括位于电源端侧的第一NPN双极晶体管的图腾柱输出级和位于地侧的第二NPN双极晶体管; 用于向第一NPN晶体管的基极提供脉冲作用的第一微分电路; 一对用于可控地驱动第二NPN晶体管的串联PMOS晶体管; 以及用于加速输出级晶体管关断的反馈MOS晶体管。电路可以用第二微分电路代替串联连接的一对PMOS晶体管。还可以实现电路的布置，其中图腾柱连接由PNP晶体管，电源端侧和地面或下拉侧的NPN或NMOS晶体管构成。利用这种电路配置，输出信号摆幅最大化，微分电路提供临时饱和以及快速恢复，从而减少传输延迟时间并实现低功耗。该设备可以由采用自举效应以及IIL（I2L）设计方案的电路来实现。

32. 发明授权

US5497023A Semiconductor memory device having separately biased wells for isolation 失效
标题翻译：半导体存储器件具有单独偏置的阱用于隔离
公开(公告)号：US5497023A
公开(公告)日：1996-03-05
申请号：US352238
申请日：1994-12-08
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikasu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikasu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0623 , H01L27/0922 , H01L27/0218 , H01L27/105 , Y10S257/901 , Y10S257/904
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

33. 发明授权

US5480932A Polypropylene resin composition and a molded article thereof 失效
标题翻译：聚丙烯树脂组合物及其模制品
公开(公告)号：US5480932A
公开(公告)日：1996-01-02
申请号：US266495
申请日：1994-06-27
申请人： Yutaka Kobayashi , Osamu Aoki , Kenji Hamabe , Atsushi Takeuchi , Takayuki Onda
发明人： Yutaka Kobayashi , Osamu Aoki , Kenji Hamabe , Atsushi Takeuchi , Takayuki Onda
IPC分类号： C08L9/00 , C08L23/10 , C08L23/16 , C08L53/00 , C08L47/00
CPC分类号： C08L23/10 , C08L53/00 , C08L23/16 , C08L9/00
摘要： A polypropylene resin composition comprising: (a) 50 to 90% by weight of polypropylene, (b) 50 to 10% by weight of an ethylene-.alpha.-olefin copolymer elastomer having a Mooney viscosity (ML 1+4 (100.degree. C.)) of 10 to 100, (c) 0.5 to 10 parts by weight per 100 parts by weight of the total of the amounts of the components (a) and (b) of a linear olefinic polymer containing hydroxyl group which is liquid at room temperature, and (d) 0.5 to 15 parts by weight per 100 parts by weight of the total of the amounts of the components (a) and (b) of a linear olefinic polymer having a melting point of about 70.degree. to about 90.degree. C. and a number-average molecular weight of 1500 to 6000 and containing hydroxyl group or carbonyl group; and a protective strip for automobiles using the polypropylene resin composition are disclosed. Coating immediately after degreasing is made possible and excellent property for coating can be provided by using the polypropylene resin composition.
摘要翻译：一种聚丙烯树脂组合物，其包含：（a）50至90重量％的聚丙烯，（b）50至10重量％的门尼粘度（ML 1 + 4（100℃）的乙烯-α-烯烃共聚物弹性体）））为10〜100，（c）相对于室内为液体的含有羟基的直链烯烃系聚合物的成分（a）和（b）的总量的100重量份，为0.5〜10重量份温度，和（d）每100重量份熔点为约70℃至约90℃的线性烯烃聚合物的组分（a）和（b）的总量的0.5至15重量份且数均分子量为1500〜6000，含有羟基或羰基; 并公开了使用该聚丙烯树脂组合物的汽车用保护带。通过使用聚丙烯树脂组合物，可以在脱脂后立即进行涂布，可以提供优异的涂布性。

34. 发明授权

US5398318A High speed, low noise output buffer with non-identical pairs of output transistors 失效
标题翻译：具有不相同输出晶体管对的高速，低噪声输出缓冲器
公开(公告)号：US5398318A
公开(公告)日：1995-03-14
申请号：US608370
申请日：1990-11-02
申请人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
发明人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/08 , H03K19/088 , H03K19/0944 , G06F13/00
CPC分类号： H03K19/09448 , H03K17/164 , H03K19/00361
摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
摘要翻译：提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

35. 发明授权

US5276648A Testing method for a semiconductor memory device 失效
标题翻译：半导体存储器件的测试方法
公开(公告)号：US5276648A
公开(公告)日：1994-01-04
申请号：US818274
申请日：1992-01-08
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译：提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

36. 发明授权

US5258644A Semiconductor device and method of manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5258644A
公开(公告)日：1993-11-02
申请号：US918133
申请日：1992-07-23
申请人： Akihiro Tamba , Yutaka Kobayashi , Tetsurou Matsumoto
发明人： Akihiro Tamba , Yutaka Kobayashi , Tetsurou Matsumoto
IPC分类号： H01L29/735 , H01L29/00
CPC分类号： H01L29/735
摘要： An improved bipolar transistor is provided which can be formed using a number of process steps which are similar to those used for forming MOSFETs. As such, the bipolar transistor is particularly useful in BiCMOS device arrangements. In accordance with one embodiment, a bipolar transistor is formed so that at least one of the emitter and collector regions has a high impurity region and a low impurity region. The collector and emitter regions of the device are formed in the base region to be spaced apart from one another, and the base electrode is arranged to cover the area of the base region between them. In an alternative embodiment, two collector regions can be provided in a base region on opposite sides of an emitter which is also formed in the base region. Two base electrodes can then be respectively provided in the areas between the two collectors and the emitter region. The bipolar transistors are particularly useful for forming a horizontal bipolar transistor structure. Because the bipolar transistors can be formed using the same types of steps used in the manufacture of MOSFETs, the manufacturing costs of the device can be reduced without sacrificing operational capabilities. This is particularly true in the manufacture of BiCMOS devices because many simultaneous manufacturing steps can be used for manufacturing the bipolar transistors and the MOSFETs.
摘要翻译：提供了一种改进的双极晶体管，其可以使用与用于形成MOSFET的那些类似的多个工艺步骤形成。因此，双极晶体管在BiCMOS器件布置中特别有用。根据一个实施例，形成双极晶体管，使得发射极和集电极区域中的至少一个具有高杂质区域和低杂质区域。器件的集电极和发射极区域形成在基极区域中以彼此间隔开，并且基极布置成覆盖它们之间的基极区域的区域。在替代实施例中，两个集电极区域可以设置在也形成在基极区域中的发射极的相对侧上的基极区域中。然后可以在两个集电极和发射极区域之间的区域中分别提供两个基极。双极晶体管特别适用于形成水平双极晶体管结构。因为可以使用与制造MOSFET相同类型的步骤来形成双极晶体管，所以可以降低器件的制造成本而不牺牲操作能力。在BiCMOS器件的制造中尤其如此，因为许多同时的制造步骤可用于制造双极晶体管和MOSFET。

37. 发明授权

US5150325A Bi-CMOS semiconductor memory device, including improved layout structure and testing method 失效
标题翻译： Bi-CMOS半导体存储器件，包括改进的布局结构和测试方法
公开(公告)号：US5150325A
公开(公告)日：1992-09-22
申请号：US496227
申请日：1990-03-20
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译：提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。读信号作为固化信号传输，然后转换为电压信号以提高读取速度。此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

38. 外观设计

USD328259S Pedometer 失效
公开(公告)号：USD328259S
公开(公告)日：1992-07-28
申请号：US520219
申请日：1990-05-04
申请人： Yutaka Kobayashi
设计人： Yutaka Kobayashi

39. 发明授权

US4962052A Method for producing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US4962052A
公开(公告)日：1990-10-09
申请号：US478050
申请日：1990-02-07
申请人： Kyoichiro Asayama , Hiroyuki Miyazawa , Yutaka Kobayashi , Seigou Yukutake
发明人： Kyoichiro Asayama , Hiroyuki Miyazawa , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L27/105 , H01L29/10 , H01L29/73 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L27/105
摘要： A method for producing a memory LSI having in its peripheral circuitry an MISFET of LDD structure and a vertical type bipolar transistor is disclosed. More particularly, an impurity for forming a low impurity concentration region of the said MISFET of LDD structure is introduced sideways of an emitter-base junction of the bipolar transistor. By the introduction of the said impurity, an effective impurity concentration near the base surface is reduced and the cut-off frequency of the bipolar transistor is improved.
摘要翻译：公开了一种在其外围电路中具有LDD结构的MISFET和垂直型双极晶体管的存储器LSI的制造方法。更具体地，用于形成LDD结构的所述MISFET的低杂质浓度区域的杂质被侧向引入双极晶体管的发射极 - 基极结。通过引入所述杂质，降低了基极表面附近的有效杂质浓度，提高了双极晶体管的截止频率。

40. 发明授权

US4657519A Plastic toy and method of manufacturing same 失效
标题翻译：塑料玩具及其制造方法
公开(公告)号：US4657519A
公开(公告)日：1987-04-14
申请号：US772884
申请日：1985-09-05
申请人： Yutaka Kobayashi
发明人： Yutaka Kobayashi
IPC分类号： A63H3/16 , A63H3/36 , A63H3/38 , A63H3/46 , A63H3/48 , A63H9/00
CPC分类号： A63H9/00 , A63H3/36 , A63H3/46
摘要： In manufacturing a toy doll conventionally, for instance, a front half constituting one half of a doll body, a rear half constituting the other half of a doll body and a set of head, hands and legs connected by a molding gate are molded separately. Thereafter, the head, hands and legs are separated from the gate one by one; the separated parts are independently arranged between the two halves one by one before fixing the two halves with the parts sandwiched therebetween. To improve the productivity, the various parts are molded, in connection with plural molding gates, at such positions that these parts are appropriately supported by and/or engageable with the front and rear halves. Therefore, it is possible to assemble the plastic toy doll immediately without separating various parts one by one from the gate before assembling the toy doll. The molding gates may be broken, after assembling, by twisting the hands or legs.
摘要翻译：在制造玩具娃娃时，例如，构成玩偶主体的一半的前半部分，构成玩偶主体的另一半的后半部分和通过模制门连接的一组头部，手和腿分别模制。此后，头，手，脚逐一与门口分开; 分离的部件在将两个部分夹在其间的部分固定之前，一个接一个地独立地设置在两个半部之间。为了提高生产率，各种部件在与多个模制浇口相关联的这些位置处被模制，这些部件被前半部和后半部适当地支撑和/或与其接合。因此，可以在组装玩具娃娃之前立即组装塑料玩具娃娃，而不必将各种零件从门上逐个分离。模制门可以在组装之后通过扭转手或腿而被破坏。

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