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31. 发明授权

US6084961A Circuit for monitoring battery voltages of telephone terminal facility, using power detector temporarily activated by ringing or off-hook signal 失效
标题翻译：用于监控电话终端设备的电池电压的电路，使用通过振铃或摘机信号暂时激活的功率检测器
公开(公告)号：US6084961A
公开(公告)日：2000-07-04
申请号：US73298
申请日：1998-05-05
申请人： Bar-Chung Hwang , Jizoo Lin , Gwo-Shu Chiou , Yung-Chow Peng
发明人： Bar-Chung Hwang , Jizoo Lin , Gwo-Shu Chiou , Yung-Chow Peng
IPC分类号： H04M19/00 , H04M1/00
CPC分类号： H04M19/00
摘要： A circuit for monitoring battery voltages of a telephone terminal facility is disclosed. This circuit mainly includes a ringing detection circuit for generating a pulse signal in response to an off-hook signal or a ringing signal, a power detecting circuit for detecting battery voltages and a latch being in series connection with the power detecting circuit for outputting a signal showing a status of the detected battery voltages. The power detecting circuit and the latch are of an edge-triggered type and are activated only when a handset of a telephone is picked up or a ringing signal is received so that both the consumed power and the voltage variations are low.
摘要翻译：公开了一种用于监视电话终端设备的电池电压的电路。该电路主要包括响应于摘机信号或振铃信号产生脉冲信号的振铃检测电路，用于检测电池电压的功率检测电路和与功率检测电路串联连接的锁存器，用于输出信号显示检测到的电池电压的状态。功率检测电路和锁存器是边缘触发型的，并且只有在接收到电话的手机或者接收到振铃信号时激活，以便消耗功率和电压变化都低。

32. 发明授权

US09287252B2 Semiconductor mismatch reduction 有权
标题翻译：半导体失配减少
公开(公告)号：US09287252B2
公开(公告)日：2016-03-15
申请号：US13048411
申请日：2011-03-15
申请人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
发明人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
IPC分类号： H01L29/12 , H01L27/02
CPC分类号： H01L27/0207
摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.
摘要翻译：公开了一种用于减小密度失配的系统和方法。一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

33. 发明申请

US20140008817A1 THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT 审中-公开
标题翻译：通过硅（TSV）隔离结构减少3D集成电路中的噪声
公开(公告)号：US20140008817A1
公开(公告)日：2014-01-09
申请号：US14024925
申请日：2013-09-12
申请人： Jaw-Juinn HORNG , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
发明人： Jaw-Juinn HORNG , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
摘要翻译：提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能通过半导体衬底传播的电噪声。隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

34. 发明授权

US07852242B2 Increasing 8B/10B coding speed using a disparity look-ahead table 有权
标题翻译：使用视差预览表增加8B / 10B编码速度
公开(公告)号：US07852242B2
公开(公告)日：2010-12-14
申请号：US12121509
申请日：2008-05-15
申请人： Wen-Hung Huang , Yung-Chow Peng
发明人： Wen-Hung Huang , Yung-Chow Peng
IPC分类号： H03M7/00
CPC分类号： H04L25/4908 , H04L25/4919
摘要： A method for encoding data packets includes providing an encoding scheme for coding source data units into encoded data units; establishing a first look-ahead table for the source data units; providing a data packet including a first source data unit and a second source data unit; encoding the first source data unit to generate a first encoded data unit; indexing the first look-ahead table using the first source data unit to determine a balancing capability of the first encoded data unit for balancing a running disparity; and encoding the second source data unit to generate a second encoded data unit using the balancing capability of the first encoded data unit.
摘要翻译：一种用于编码数据分组的方法包括提供用于将源数据单元编码为编码数据单元的编码方案; 为源数据单元建立第一个预先表; 提供包括第一源数据单元和第二源数据单元的数据分组; 编码所述第一源数据单元以生成第一编码数据单元; 使用所述第一源数据单元索引所述第一预览表，以确定所述第一编码数据单元的平衡能力以平衡运行的差异; 以及使用所述第一编码数据单元的平衡能力对所述第二源数据单元进行编码以生成第二编码数据单元。

35. 发明授权

US06864756B2 Automatic gain control circuit for controlling start-up time of oscillator and method thereof 失效
标题翻译：用于控制振荡器启动时间的自动增益控制电路及其方法
公开(公告)号：US06864756B2
公开(公告)日：2005-03-08
申请号：US10604652
申请日：2003-08-07
申请人： Yung-Chow Peng
发明人： Yung-Chow Peng
IPC分类号： H03B5/00 , H03B5/06 , H03D11/04 , H03L1/00 , H03L3/00
CPC分类号： H03B5/06 , H03D11/04 , H03L3/00
摘要： An automatic gain control circuit for controlling a start-up time of an oscillator and a method thereof are provided. An oscillation detection unit is used to detect the start-up time of the oscillator. In addition, a control unit is used to move the start-up time of the oscillator forward when the start-up time of the oscillator is later than a first predetermined time point. Moreover, when the start-up time of the oscillator is earlier than a second predetermined time point, the start-up time of the oscillator is delayed.
摘要翻译：提供了一种用于控制振荡器启动时间的自动增益控制电路及其方法。振荡检测单元用于检测振荡器的启动时间。此外，当振荡器的启动时间晚于第一预定时间点时，控制单元用于向前移动振荡器的启动时间。此外，当振荡器的启动时间早于第二预定时间点时，振荡器的启动时间被延迟。

36. 发明授权

US06677785B1 Power level detection circuit 失效
标题翻译：功率电平检测电路
公开(公告)号：US06677785B1
公开(公告)日：2004-01-13
申请号：US10202184
申请日：2002-07-24
申请人： Yung-Chow Peng , Li-Yueh Wang
发明人： Yung-Chow Peng , Li-Yueh Wang
IPC分类号： H03K500
CPC分类号： H03K5/084 , G01R19/16547 , H03K17/223
摘要： A power level detection circuit detects the voltage level of a power source. The power level detection circuit has a first voltage level detector having an input coupled to the power source and outputting a first signal representative of an upper boundary, a second voltage level detector having an input coupled to the power source and outputting a second signal representative of a desired detection level, and a third voltage level detector having an input coupled to the power source and outputting a third signal representative of a lower boundary. The power level detection circuit also has a control circuit coupled to the first, second and third signals for outputting a power level detection signal if there is a change in the second signal, and when the power level is greater than the level of the third signal and less than the level of the first signal.
摘要翻译：功率电平检测电路检测电源的电压电平。功率电平检测电路具有第一电压电平检测器，其具有耦合到电源的输入并输出表示上边界的第一信号，第二电压电平检测器具有耦合到电源的输入端，并输出代表期望的检测电平，以及具有耦合到电源的输入并输出表示下边界的第三信号的第三电压电平检测器。功率电平检测电路还具有耦合到第一，第二和第三信号的控制电路，用于在第二信号有变化时输出功率电平检测信号，并且当功率电平大于第三信号的电平时并且小于第一信号的电平。

37. 发明授权

US06628160B2 Semiconductor integrated circuit for low-voltage high-speed operation 有权
标题翻译：半导体集成电路用于低压高速运行
公开(公告)号：US06628160B2
公开(公告)日：2003-09-30
申请号：US09798977
申请日：2001-03-06
申请人： Shi-Tron Lin , Yung-Chow Peng
发明人： Shi-Tron Lin , Yung-Chow Peng
IPC分类号： H03K301
CPC分类号： H03K19/01707 , H01L27/092 , H01L29/78609 , H03K19/0016
摘要： For low-voltage and high-speed operation of a MOSFET in an integrated circuit, a small voltage is applied to a source node, causing slight forward bias of the source junction and thereby reducing its threshold voltage. Due to the combined effects of the bias at the source node and a body effect, the reduction in threshold voltage is larger than the absolute value of the source voltage being applied. A performance improvement over simply applying a bias voltage to the body (well) results. Detection of an event can be used to apply the performance boost to a critical path in the integrated circuit only when needed. Upon detection of a logic event, which determines that a signal will propagate through the critical path shortly thereafter, the source-node bias for circuit elements in the critical path can be adjusted in time for a speed improvement. However, the source remains at another potential when no signal is passing through the critical-path, to save power when not boosting speed.
摘要翻译：对于集成电路中的MOSFET的低电压和高速操作，向源节点施加小的电压，从而导致源极结的轻微的正向偏压，从而降低其阈值电压。由于源节点偏置和物体效应的组合效应，阈值电压的降低大于施加的源极电压的绝对值。通过简单地将偏置电压施加到身体（井），可以提高性能。可以使用事件的检测来仅在需要时将性能提升应用于集成电路中的关键路径。当检测到逻辑事件确定信号在此后不久将传播通过关键路径时，关键路径中的电路元件的源节点偏置可以及时调整以提高速度。然而，当没有信号通过关键路径时，源保持在另一个潜力，以便在不提升速度时节省功率。

38. 发明授权

US06516290B1 Method for measuring the nonlinearity of an analog front end system 失效
标题翻译：测量模拟前端系统非线性的方法
公开(公告)号：US06516290B1
公开(公告)日：2003-02-04
申请号：US09378619
申请日：1999-08-20
申请人： Yung-Chow Peng
发明人： Yung-Chow Peng
IPC分类号： H04B1500
CPC分类号： H03M1/109 , H03M1/12
摘要： A method for accurately measuring the integral nonlinearity (INL) and differential nonlinearity (DNL) of an analog front end (AFE) system, such as an analog/digital converter (ADC), is provided. In particular, the method eliminates the need for well-calibrated equipment and an accurate signal source. Differing from conventional approaches, according to the invention, the INL of the AFE system is obtained by directly transferring the output of the AFE system rather than by accumulating the DNL. Therefore, the INL of the measured AFE system according to the invention is only slightly affected by inputted signal source.
摘要翻译：提供了一种用于精确测量模拟前端（AFE）系统（如模拟/数字转换器（ADC））的积分非线性（INL）和差分非线性（DNL）的方法。特别地，该方法消除了对精确校准的设备和准确的信号源的需要。与传统方法不同，根据本发明，AFE系统的INL通过直接传送AFE系统的输出而不是通过累积DNL获得。因此，根据本发明的测量的AFE系统的INL仅受输入信号源的稍微影响。

39. 发明授权

US6067336A Charge pump circuit 失效
标题翻译：电荷泵电路
公开(公告)号：US6067336A
公开(公告)日：2000-05-23
申请号：US164842
申请日：1998-10-01
申请人： Yung-Chow Peng
发明人： Yung-Chow Peng
IPC分类号： H03L7/08 , H03L7/081 , H03L7/089 , H03L7/16 , H03D3/24
CPC分类号： H03L7/0896 , H03L7/0812 , H03L7/16 , H03L2207/14 , H03L7/0802
摘要： A charge pump includes a constant current source, a charging field effect transistor (FET) and a discharging FET coupled to mirror a current in the constant current source, a first pair of switching transistors controlling a charging current flow between a charging path and a first standby path, a second pair of switching transistors controlling a discharging current flow between a discharging path and a second standby path, a first and a second pairs of transistors isolating output and input of the charge pump and keeping unchanged the drain voltages of the charging and the discharging FETs. The two pairs of switching transistors in conjunction with the two pairs of transistors act to keep the charging and the discharging currents always on. Accordingly, the switching performance of the disclosed charge pump is much better than prior arts without using current-steering amplifier and is capable of high frequency operation. In addition, charge feedthrough, jitters, and unbalanced output waveform is not going to be significant in the invention. Consequently, the invention provides a device-saving charge pump supplying matched up and down current pulse without charge feedthrough.
摘要翻译：电荷泵包括恒流源，充电场效应晶体管（FET）和耦合以反射恒流源中的电流的放电FET;第一对开关晶体管，控制充电路径和第一控制放电路径和第二备用路径之间的放电电流的第二对开关晶体管，隔离电荷泵的输出和输入的第一和第二对晶体管，并保持充电的漏极电压和放电FET。结合两对晶体管的两对开关晶体管用于保持充电和放电电流始终导通。因此，所公开的电荷泵的开关性能比现有技术好得多，而不使用电流导向放大器，并且能够进行高频操作。此外，在本发明中，充电馈通，抖动和不平衡输出波形并不显着。因此，本发明提供了一种节省设备的电荷泵，其提供匹配的上下电流脉冲，而无需充电馈通。

40. 发明授权

US08904326B2 Semiconductor device design method, system and computer program product 有权
标题翻译：半导体器件设计方法，系统和计算机程序产品
公开(公告)号：US08904326B2
公开(公告)日：2014-12-02
申请号：US13539258
申请日：2012-06-29
申请人： Mu-Jen Huang , Chih Chi Hsiao , Wei-Ting Lin , Tsung-Hsin Yu , Chien-Wen Chen , Yung-Chow Peng
发明人： Mu-Jen Huang , Chih Chi Hsiao , Wei-Ting Lin , Tsung-Hsin Yu , Chien-Wen Chen , Yung-Chow Peng
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/505 , G06F17/5072 , G06F17/5077 , G06F17/5081
摘要： In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.
摘要翻译：在由至少一个处理器执行的半导体器件设计方法中，所述至少一个处理器提取半导体器件的布局中的至少一个电气部件的位置数据。由至少一个处理器提取与所述至少一个电气部件相关联并且基于所述半导体器件的操作的模拟的电压数据。基于所提取的位置数据，所提取的电压数据由所述至少一个处理器并入所述布局中以生成所述半导体器件的修改的布局。

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