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1. 发明授权

US6084961A Circuit for monitoring battery voltages of telephone terminal facility, using power detector temporarily activated by ringing or off-hook signal 失效
标题翻译：用于监控电话终端设备的电池电压的电路，使用通过振铃或摘机信号暂时激活的功率检测器
公开(公告)号：US6084961A
公开(公告)日：2000-07-04
申请号：US73298
申请日：1998-05-05
申请人： Bar-Chung Hwang , Jizoo Lin , Gwo-Shu Chiou , Yung-Chow Peng
发明人： Bar-Chung Hwang , Jizoo Lin , Gwo-Shu Chiou , Yung-Chow Peng
IPC分类号： H04M19/00 , H04M1/00
CPC分类号： H04M19/00
摘要： A circuit for monitoring battery voltages of a telephone terminal facility is disclosed. This circuit mainly includes a ringing detection circuit for generating a pulse signal in response to an off-hook signal or a ringing signal, a power detecting circuit for detecting battery voltages and a latch being in series connection with the power detecting circuit for outputting a signal showing a status of the detected battery voltages. The power detecting circuit and the latch are of an edge-triggered type and are activated only when a handset of a telephone is picked up or a ringing signal is received so that both the consumed power and the voltage variations are low.
摘要翻译：公开了一种用于监视电话终端设备的电池电压的电路。该电路主要包括响应于摘机信号或振铃信号产生脉冲信号的振铃检测电路，用于检测电池电压的功率检测电路和与功率检测电路串联连接的锁存器，用于输出信号显示检测到的电池电压的状态。功率检测电路和锁存器是边缘触发型的，并且只有在接收到电话的手机或者接收到振铃信号时激活，以便消耗功率和电压变化都低。

2. 发明授权

US5627739A Regulated charge pump with low noise on the well of the substrate 失效
标题翻译：衬底上的低噪声调节电荷泵
公开(公告)号：US5627739A
公开(公告)日：1997-05-06
申请号：US630879
申请日：1996-04-02
申请人： Peng Yung-Chow , Jizoo Lin
发明人： Peng Yung-Chow , Jizoo Lin
IPC分类号： H02M3/07 , H02M3/18
CPC分类号： H02M3/07
摘要： A regulated charge pump is provided to boost an amount of voltage while minimizing the well voltage fluctuation during the operation. The charge pump includes a charge pump core which has a first transistor, a second, a third transistor and an integration circuit. The first transistor has a first current electrode for receiving the first power supply voltage and a second current electrode coupled to the first terminal of the charging capacitor. The second transistor has a first current electrode coupled to a second terminal of the charging capacitor, a control electrode and a second electrode for receiving a second power supply voltage. The second transistor is proportionately conductive during the first predetermined time period. The third transistor has a first current electrode for receiving the first power supply voltage, and a second current electrode coupled to the second terminal of the charging capacitor. The third transistor is conductive during the second predetermined time period. The integration circuit is coupled to the control electrode of the second transistor, for changing the second voltage proportionately in response to an integration of a difference between a proportional voltage and a reference voltage by altering a conductivity of the second transistor.
摘要翻译：提供稳压电荷泵以提高电压量，同时最小化操作期间的阱电压波动。电荷泵包括具有第一晶体管，第二，第三晶体管和积分电路的电荷泵芯。第一晶体管具有用于接收第一电源电压的第一电流电极和耦合到充电电容器的第一端子的第二电流电极。第二晶体管具有耦合到充电电容器的第二端子的第一电流电极，用于接收第二电源电压的控制电极和第二电极。第二晶体管在第一预定时间段期间成比例地导电。第三晶体管具有用于接收第一电源电压的第一电流电极和耦合到充电电容器的第二端子的第二电流电极。第三晶体管在第二预定时间段期间导通。积分电路耦合到第二晶体管的控制电极，用于通过改变第二晶体管的电导率来响应于比例电压和参考电压之间的差异的积分而成比例地改变第二电压。

3. 发明授权

US06795052B2 Voltage reference with controllable temperature coefficients 有权
标题翻译：具有可控温度系数的参考电压
公开(公告)号：US06795052B2
公开(公告)日：2004-09-21
申请号：US09885207
申请日：2001-06-20
申请人： Jizoo Lin , Jong-Ping Lee , Yung-Peng Hwang
发明人： Jizoo Lin , Jong-Ping Lee , Yung-Peng Hwang
IPC分类号： G09G336
CPC分类号： G09G3/3696 , G09G2320/041
摘要： A voltage reference circuit and method for producing a voltage as a reference voltage for a liquid crystal display (LCD) panel. The voltage reference circuit with controllable temperature coefficients includes a logic operation unit and a voltage selection circuit. The logic operation unit receives a command corresponding to the temperature coefficient of an LCD panel and provides a selection signal according to the command. The selection signal is applied to the voltage selection circuit. Depending on the selection signal, the voltage selection circuit generates a selected voltage which is used to produce a reference voltage.
摘要翻译：一种用于产生用于液晶显示（LCD）面板的基准电压的电压参考电路和方法。具有可控温度系数的电压参考电路包括逻辑运算单元和电压选择电路。逻辑运算单元接收与LCD面板的温度系数对应的指令，并根据该命令提供选择信号。选择信号被施加到电压选择电路。根据选择信号，电压选择电路产生用于产生参考电压的选定电压。

4. 发明授权

US6052422A Analog signal offset cancellation circuit and method 失效
标题翻译：模拟信号偏移消除电路及方法
公开(公告)号：US6052422A
公开(公告)日：2000-04-18
申请号：US036178
申请日：1998-03-06
申请人： Jizoo Lin
发明人： Jizoo Lin
IPC分类号： H04L7/033 , H04L7/00
CPC分类号： H04L7/0331
摘要： An analog signal offset cancellation circuit comprising a front end device, a comparator, a sampling device, a resampling clock generator and a recovery data generator is disclosed. In this offset cancellation circuit, the front end device receives an input analog signal. The comparator then compares the input analog signal with a threshold voltage to obtain an output binary signal. The sampling device samples the output binary signal by a sampling signal having a frequency N times that of the output binary signal to obtain sample data. The resampling clock generator then continually reads 2N samples of the sample data and outputs a two period resampling clock with its rising and falling edges determined by the edges and the number of uninterrupted logic one samples of the 2N samples. The resampling clock remains unchanged when the 2N samples are all logic one or all logic zero. The recovery data generator then samples the output binary signal using the resampling clock to obtain recovery data.
摘要翻译：公开了一种包括前端装置，比较器，采样装置，重采样时钟发生器和恢复数据发生器的模拟信号偏移消除电路。在该偏移消除电路中，前端装置接收输入的模拟信号。比较器然后将输入的模拟信号与阈值电压进行比较，以获得输出二进制信号。采样装置用输出二进制信号的N倍的采样信号对输出的二进制信号进行采样，以获得样本数据。重采样时钟发生器然后连续读取采样数据的2N个样本，并输出两个周期重采样时钟，其上升沿和下降沿由边缘和2N个样本的不间断逻辑的一个采样数确定。当2N个样本都是逻辑1或所有逻辑0时，重采样时钟保持不变。然后，恢复数据生成器使用重采样时钟对输出二进制信号进行采样，以获得恢复数据。

5. 发明授权

US5987120A Device for identifying line reversal/ringing signal of a telephone set 失效
标题翻译：用于识别电话机的线路反转/振铃信号的装置
公开(公告)号：US5987120A
公开(公告)日：1999-11-16
申请号：US980725
申请日：1997-12-01
申请人： Bar-Chung Hwang , Jizoo Lin
发明人： Bar-Chung Hwang , Jizoo Lin
IPC分类号： H04M1/82 , H04M19/04 , H04M1/00
CPC分类号： H04M1/82 , H04M19/04
摘要： A device for identifying a line reversal signal and a ringing signal of a telephone set having a built-in ringing detection circuit includes a counter, a comparator and a latch connected with each other in series. The device can determine whether a signal on line is the line reversal signal or the ringing signal of the telephone set without using an installed CPU or a timer thereof, so as to save power and reduce the load of the CPU.
摘要翻译：用于识别具有内置振铃检测电路的电话机的线路反转信号和振铃信号的装置包括彼此串联连接的计数器，比较器和锁存器。该装置可以确定在线信号是线路反转信号还是电话机的振铃信号，而不使用已安装的CPU或其定时器，以节省功率并减少CPU的负载。

6. 发明授权

US5446416A Time acquisition system with dual-loop for independent frequency phase lock 失效
标题翻译：具有双回路用于独立频率锁相的时间采集系统
公开(公告)号：US5446416A
公开(公告)日：1995-08-29
申请号：US139548
申请日：1993-10-20
申请人： Jizoo Lin , Hsan-Fong Lin , Ret-Bean Lee , Chorng-Kuang Wang
发明人： Jizoo Lin , Hsan-Fong Lin , Ret-Bean Lee , Chorng-Kuang Wang
IPC分类号： H03L7/07 , H03L7/113 , H03L7/06
CPC分类号： H03L7/113 , H03L7/07
摘要： A time acquisition system is disclosed with dual independent frequency and phase lock loops, each containing a dedicated voltage controlled oscillator (VCO). The frequency lock loop (FLL) outputs a frequency bias signal, used for coarse frequency lock-up, only when the difference frequency between the input signal and the FLL VCO is outside a predetermined frequency band -.DELTA..omega..sub.L to .DELTA..omega..sub.L. Significantly, the frequency bias signal is equal to zero when the difference frequency between the input signal and the FLL VCO is inside the frequency band -.DELTA..omega..sub.L to .DELTA..omega..sub.L. The phase lock loop (PLL) provides a phase bias signal, used for fine tuning lock-up, when the difference frequency between the input signal and the PLL VCO is inside the predetermined frequency band -.DELTA..omega..sub.L to .DELTA..omega..sub.L. Therefore, there is no interaction between loops during the final phase tuning lock-up.
摘要翻译：公开了具有双独立频率和锁相环的时间采集系统，每个包含专用的压控振荡器（VCO）。只有当输入信号和FLL VCO之间的差分频率超出预定频带（DELTA omega L to DELTA omega L）时，频率锁定环路（FLL）才会输出用于粗频率锁定的频率偏置信号。当输入信号和FLL VCO之间的差分频率在频带-DTATAωL到DELTAωLL内时，频率偏置信号等于零。锁相环（PLL）提供相位偏置信号，用于当输入信号和PLL VCO之间的差分频率在预定频带-DTATAωL到DELTAωLL内时，微调锁定。因此，在最终相位调谐锁定期间，循环之间没有相互作用。

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