专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07524757B2 Method for manufacturing multi-level transistor comprising forming selective epitaxial growth layer 有权
标题翻译：制造多级晶体管的方法，包括形成选择性外延生长层
公开(公告)号：US07524757B2
公开(公告)日：2009-04-28
申请号：US11485485
申请日：2006-07-13
申请人： Sung-jun Kim , Chang-ki Hong , Bo-un Yoon , Jae-kwang Choi
发明人： Sung-jun Kim , Chang-ki Hong , Bo-un Yoon , Jae-kwang Choi
IPC分类号： H01L21/4763
CPC分类号： H01L21/8221 , H01L27/0688 , H01L27/12
摘要： A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer on the substrate, and forming a preliminary second SEG layer and a dummy layer, wherein the preliminary second SEG layer is formed directly on only the first SEG layer and a portion of the first insulating layer formed on the cell region of the substrate, and wherein the dummy layer is formed on the peripheral region of the substrate. The method further includes planarizing the preliminary second SEG layer using the dummy layer as a stop layer to form a second SEG layer, forming a second active region from the second SEG layer formed on a first insulating layer, and forming a second transistor on the second active region.
摘要翻译：一种在衬底上制造多电平晶体管的方法。该方法包括在第一有源区上形成第一晶体管，在衬底上形成第一选择性外延生长（SEG）层，形成初步的第二SEG层和虚设层，其中初步的第二SEG层直接形成所述第一SEG层和形成在所述基板的单元区域上的所述第一绝缘层的一部分，并且所述虚设层形成在所述基板的周边区域上。该方法还包括使用虚设层作为停止层平坦化初步的第二SEG层以形成第二SEG层，从形成在第一绝缘层上的第二SEG层形成第二有源区，并在第二绝缘层上形成第二晶体管活跃区域。

32. 发明申请

US20080206985A1 Method of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20080206985A1
公开(公告)日：2008-08-28
申请号：US11878508
申请日：2007-07-25
申请人： Chae-Iyoung Kim , Chang-Ki Hong , Bo-un Yoon , Sung-ho Shin , Byoung-ho Kwon
发明人： Chae-Iyoung Kim , Chang-Ki Hong , Bo-un Yoon , Sung-ho Shin , Byoung-ho Kwon
IPC分类号： H01L21/44
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/7688 , Y10S438/947
摘要： Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region.
摘要翻译：提供制造半导体器件的方法。所述方法包括在具有第一区域和第二区域的半导体衬底上形成层间绝缘层。第一接触塞可以形成在第二区域的一部分上以填充多个第一接触孔。多个第一接触掩模层和多个第一伪掩模层可以形成在层间绝缘层上。第一接触掩模层可以形成在第一区域中。第一虚拟掩模层可以形成在第二区域中。可以在两个相邻的第一接触掩模层之间形成多个第二接触掩模层。可以在两个相邻的第一虚拟掩模层之间形成多个第二虚拟掩模层。可以使用第一接触掩模层和第二接触掩模层作为蚀刻停止层来蚀刻层间绝缘层，以形成穿过形成在第一区域中的层间绝缘层的多个第二接触孔。

33. 发明申请

US20070293048A1 Polishing slurry 审中-公开
标题翻译：抛光浆
公开(公告)号：US20070293048A1
公开(公告)日：2007-12-20
申请号：US11812140
申请日：2007-06-15
申请人： Jon-won Lee , Chang-ki Hong , Bo-un Yoon
发明人： Jon-won Lee , Chang-ki Hong , Bo-un Yoon
IPC分类号： H01L21/461 , B24D3/02 , C09K3/14
CPC分类号： H01L21/7684 , C09G1/02 , C09K3/1409 , C09K3/1463 , H01L21/3212
摘要： A polishing slurry, including an oxidizer, a corrosion inhibitor, and a polishing rate enhancer, wherein the polishing rate enhancer is a heterocyclic compound having at least one nitrogen in the ring, and the nitrogen is not directly bonded to a hydrogen atom which is mostly dissociated in the slurry.
摘要翻译：一种抛光浆料，包括氧化剂，缓蚀剂和抛光速率增强剂，其中抛光速率增强剂是环中至少有一个氮的杂环化合物，并且氮不直接键合到主要是氢原子在浆液中解离。

34. 发明授权

US07196010B2 Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same 失效
公开(公告)号：US07196010B2
公开(公告)日：2007-03-27
申请号：US10639541
申请日：2003-08-12
申请人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phil Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
发明人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phil Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
IPC分类号： H01L21/302
CPC分类号： H01L21/76224 , B24B37/044 , C09G1/02 , H01L21/31053
摘要： A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

35. 发明授权

US06914001B2 Chemical/mechanical polishing slurry, and chemical mechanical polishing process and shallow trench isolation process employing the same 失效
标题翻译：化学/机械抛光浆料和化学机械抛光工艺以及采用其的浅沟槽隔离工艺
公开(公告)号：US06914001B2
公开(公告)日：2005-07-05
申请号：US10351539
申请日：2003-01-27
申请人： Jong-won Lee , Jae-dong Lee , Bo-un Yoon , Sang-rok Hah
发明人： Jong-won Lee , Jae-dong Lee , Bo-un Yoon , Sang-rok Hah
IPC分类号： B24B57/02 , B24B37/00 , C09G1/02 , C09K3/14 , H01L21/304 , H01L21/3105 , H01L21/302
CPC分类号： H01L21/31053 , C09G1/02 , C09K3/1463
摘要： A CMP oxide slurry includes an aqueous solution containing abrasive particles and two or more different passivation agents. Preferably, the aqueous solution is made up of deionized water, and the abrasive particles are a metal oxide selected from the group consisting of ceria, silica, alumina, titania, zirconia and germania. Also, a first passivation agent may be an anionic, cationic or nonionic surfactant, and a second passivation agent may be a phthalic acid and its salts. In one example, the first passivation agent is poly-vinyl sulfonic acid, and the second passivation agent is potassium hydrogen phthalate. The slurry exhibits a high oxide to silicon nitride removal selectivity.
摘要翻译： CMP氧化物浆料包括含有磨料颗粒和两种或更多种不同钝化剂的水溶液。优选地，水溶液由去离子水组成，磨料颗粒是选自二氧化铈，二氧化硅，氧化铝，二氧化钛，氧化锆和氧化锗的金属氧化物。此外，第一钝化剂可以是阴离子，阳离子或非离子表面活性剂，第二钝化剂可以是邻苯二甲酸及其盐。在一个实例中，第一钝化剂是聚乙烯基磺酸，第二钝化剂是邻苯二甲酸氢钾。该浆料表现出高的氧化物与氮化硅的去除选择性。

36. 发明授权

US06716732B2 Method for fabricating a contact pad of semiconductor device 有权
标题翻译：制造半导体器件接触焊盘的方法
公开(公告)号：US06716732B2
公开(公告)日：2004-04-06
申请号：US09986445
申请日：2001-11-08
申请人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Sang-rok Hah
发明人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Sang-rok Hah
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/76895
摘要： A method of fabricating a contact pad of a semiconductor device is disclosed. The method includes forming a stopping layer over the semiconductor substrate. An interdielectric layer is formed over the stopping layer, and the interdielectric layer is planarized to expose at least a gate upper dielectric layer by using a material which exhibits a high-polishing selectivity with respect to the interdielectric layer. The interdielectric layer is etched in a region in which a contact pad will be formed on the semiconductor substrate. A conductive material is deposited on the semiconductor substrate. Finally, planarizing is carried out using a material which exhibits a high-polishing selectivity of the upper dielectric layer with respect to the conductive material.
摘要翻译：公开了制造半导体器件的接触焊盘的方法。该方法包括在半导体衬底上形成阻挡层。在停止层上形成介电层，并且通过使用相对于介电层表现出高抛光选择性的材料，使介电层平坦化以至少暴露出栅极上电介质层。在其中将在半导体衬底上形成接触焊盘的区域中蚀刻介电层。导电材料沉积在半导体衬底上。最后，使用表现出相对于导电材料的上电介质层的高抛光选择性的材料进行平面化。

37. 发明授权

US06517412B2 Method of controlling wafer polishing time using sample-skip algorithm and wafer polishing using the same 有权
公开(公告)号：US06517412B2
公开(公告)日：2003-02-11
申请号：US09951506
申请日：2001-09-14
申请人： Jae-dong Lee , Bo-un Yoon , Kyoung-mo Yang , Sang-rok Hah
发明人： Jae-dong Lee , Bo-un Yoon , Kyoung-mo Yang , Sang-rok Hah
IPC分类号： B24B4900
CPC分类号： B24B37/013 , B24B37/042 , B24B49/02
摘要： A method of controlling a wafer polishing time using a sample-skip algorithm and a method of polishing a wafer using the same are provided. According to the method of controlling a wafer polishing time, a chemical mechanical polishing (CMP) process is performed on a plurality of wafers of an n-th lot among a plurality of lots, each lot consisting of a plurality of wafers, for a time &Dgr;t(n), to calculate the amount removed &Dgr;ToxP(n) from a polished layer on the wafer. The removal rate RRb(n) of a layer on a blanket wafer is calculated from the amount removed &Dgr;ToxP(n). A CMP time &Dgr;t(n+1) is determined for wafers of an n+1-th lot using the relationship equation &Dgr;t(n+1)={&Dgr;ToxT(n+1)+A}/RRb(n) where “A” is a constant and &Dgr;ToxT(n+1) is the target amount of a layer to be removed from a wafer of an n+1-th lot.

38. 发明授权

US06335287B1 Method of forming trench isolation regions 有权
标题翻译：形成沟槽隔离区域的方法
公开(公告)号：US06335287B1
公开(公告)日：2002-01-01
申请号：US09637788
申请日：2000-08-11
申请人： Hong-kyu Hwang , Bo-un Yoon , Kyu-hwan Chang , Sang-rok Hah
发明人： Hong-kyu Hwang , Bo-un Yoon , Kyu-hwan Chang , Sang-rok Hah
IPC分类号： H01L12302
CPC分类号： H01L21/76229 , H01L21/31053 , H01L21/31055
摘要： To form isolation trenches on a semiconductor substrate, chemical mechanical polishing (CMP) stopping patterns are formed on the substrate, and the substrate is then etched using the CMP stopping patterns as a mask. Then an insulating material is deposited to fill the trenches and cover the CMP stopping patterns. The insulating material is etched using a CMP process until the CMP stopping patterns become exposed, and is then etched using a wet or dry etching process. The wet or dry etching is continued until protruding insulating material above a surface of the substrate is a predetermined thickness, which corresponds to an amount of the insulating material that is etched during removal of the CMP stopping patterns and during intermediate processes prior to formation of a gate oxide layer.
摘要翻译：为了在半导体衬底上形成隔离沟槽，在衬底上形成化学机械抛光（CMP）停止图案，然后使用CMP停止图案作为掩模蚀刻衬底。然后沉积绝缘材料以填充沟槽并覆盖CMP停止图案。使用CMP工艺蚀刻绝缘材料，直到CMP停止图案露出，然后使用湿法或干蚀刻工艺进行蚀刻。继续进行湿法或干蚀刻蚀刻，直到基片表面上方的突出的绝缘材料为预定的厚度，这对应于在去除CMP停止图案期间以及在形成CMP停止图案之间的中间工艺期间被蚀刻的绝缘材料的量栅氧化层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式