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31. 发明授权

US06320361B2 Buffer device with dual supply voltage for low supply voltage applications 失效
标题翻译：用于低电源电压应用的双电源电压缓冲器件
公开(公告)号：US06320361B2
公开(公告)日：2001-11-20
申请号：US09736984
申请日：2000-12-13
申请人： Vincenzo Dima , Lorenzo Bedarida , Antonino Geraci , Simone Bartoli
发明人： Vincenzo Dima , Lorenzo Bedarida , Antonino Geraci , Simone Bartoli
IPC分类号： G05F140
CPC分类号： G05F3/242
摘要： An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.
摘要翻译：一种具有第一和第二电源电压基准的输出缓冲器装置，该第一参考电压值低于第二电压基准。输出缓冲器件包括第一和第二互补MOS晶体管，这些晶体管串联连接在一个电源电压基准和另一个电压基准之间，栅极端子连接在一起并连接到该缓冲器件的输入端，并且具有漏极连接在一起的端子和缓冲器的输出端子。有利地，第一晶体管连接到第一电源电压基准。此外，输出缓冲器件包括与第一MOS晶体管相同类型的至少一个额外的驱动MOS晶体管，并且放置在第二电源电压基准和缓冲器件的输出端之间。

32. 发明授权

US5994948A CMOS twin-tub negative voltage switching architecture 失效
标题翻译： CMOS双槽负压开关架构
公开(公告)号：US5994948A
公开(公告)日：1999-11-30
申请号：US921930
申请日：1997-08-27
申请人： Simone Bartoli , Antonio Russo , Mauro Luigi Sali
发明人： Simone Bartoli , Antonio Russo , Mauro Luigi Sali
IPC分类号： G11C16/30 , G05F1/10
CPC分类号： G11C16/30
摘要： A CMOS twin-tub negative voltage switching architecture is for a non-volatile memory device and includes a negative voltage multiplier for generating a increased voltage value starting from a single main power supply. A voltage regulator feedback is connected to the voltage multiplier for regulating the generated negative voltage value; and a plurality of independent switch circuits each one receiving as an input the negative voltage value and producing as an output a predetermined local negative voltage.
摘要翻译： CMOS双槽负电压开关结构用于非易失性存储器件，并且包括用于从单个主电源开始产生增加的电压值的负电压倍增器。电压调节器反馈连接到电压倍增器，用于调节产生的负电压值; 以及多个独立的开关电路，每个独立的开关电路每个接收负电压值作为输入，并产生预定的局部负电压作为输出。

33. 发明申请

US20130094295A1 MEMORY DEVICE IN PARTICULAR EXTRA ARRAY CONFIGURED THEREIN FOR CONFIGURATION AND REDUNDANCY INFORMATION 失效
标题翻译：在配置和冗余信息中配置的特殊外部阵列中的存储设备
公开(公告)号：US20130094295A1
公开(公告)日：2013-04-18
申请号：US13275708
申请日：2011-10-18
申请人： Simone Bartoli , Mauro Pagliato , Diego Della Mina
发明人： Simone Bartoli , Mauro Pagliato , Diego Della Mina
IPC分类号： G11C16/08
CPC分类号： G11C29/789
摘要： Disclosed herein is a device that includes a plurality of first word lines each extending from an associated one of the first terminals in a second direction toward to the second terminals and terminating between the first and second terminals, the second direction being substantially perpendicular to the first direction, and a plurality of second word lines each extending from an associated one of the second terminals in a third direction toward to the first terminals and terminating near to an end of an associated one of the first word lines, the third direction being opposite to the second direction, each of the second word lines being substantially aligned with an associated one of the first word lines.
摘要翻译：本文公开了一种装置，其包括多个第一字线，每个第一字线从第一端子中的相关联的一个在第二方向朝向第二端子延伸并且终止于第一和第二端子之间，第二方向基本上垂直于第一方向和多个第二字线，每个第二字线在第三方向上从相关联的一个第二端子延伸到第一端子并且终止于相关联的第一字线之一的端部，第三方向与第一方向相反所述第二方向，所述第二字线中的每一条基本上与所述第一字线中的相关联的一条对齐。

34. 发明申请

US20080170455A1 Compensated current offset in a sensing circuit 有权
标题翻译：感测电路中的补偿电流偏移
公开(公告)号：US20080170455A1
公开(公告)日：2008-07-17
申请号：US11652742
申请日：2007-01-12
申请人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
发明人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
IPC分类号： G11C7/08
CPC分类号： G11C7/062 , G11C7/02 , G11C7/067 , G11C16/26 , G11C2207/063
摘要： A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.
摘要翻译：具有电流偏移功能的感测电路。在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

35. 发明授权

US07283396B2 System and method for matching resistance in a non-volatile memory 有权
标题翻译：用于在非易失性存储器中匹配电阻的系统和方法
公开(公告)号：US07283396B2
公开(公告)日：2007-10-16
申请号：US11193924
申请日：2005-07-28
申请人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
发明人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译：用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。参考矩阵耦合到存储器矩阵并具有参考单元。逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

36. 发明申请

US20070076476A1 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US20070076476A1
公开(公告)日：2007-04-05
申请号：US11635160
申请日：2006-12-07
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre' , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre' , Andrea Sacco
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C5/145 , G11C11/5628 , G11C16/04 , G11C16/30 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于为存储器单元编程提供调节的编程电压，用于编程路径电压降的调节的编程电压。

37. 发明申请

US20070047325A1 Method and apparatus for discharging a memory cell in a memory device after an erase operation 有权
标题翻译：在擦除操作之后，用于在存储器件中放电存储单元的方法和装置
公开(公告)号：US20070047325A1
公开(公告)日：2007-03-01
申请号：US11583625
申请日：2006-10-18
申请人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre
发明人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre
IPC分类号： G11C16/06
CPC分类号： G11C16/12 , G11C16/10 , G11C16/22
摘要： A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.
摘要翻译：一种用于对存储器件中的存储单元进行放电的方法和装置。在一个实施方式中，存储单元包括具有第一板和第二板的电容器，并且该方法包括首先通过第一放电电路对电容器的第一板进行放电，并通过第二放电电路对电容器的第二板进行放电。在初始放电之后，该方法还包括通过将电容器的第一板和电容器的第二板耦合到地将电容器的第一板和电容器的第二板完全放电。

38. 发明授权

US07184311B2 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US07184311B2
公开(公告)日：2007-02-27
申请号：US11123754
申请日：2005-05-05
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C7/04 , G11C16/04 , G11C16/12 , G11C16/30 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于提供用于存储器单元编程的调节编程电压，用于编程路径电压降的校准编程电压并补偿温度变化。

39. 发明授权

US06854040B1 Non-volatile memory device with burst mode reading and corresponding reading method 有权
标题翻译：具有突发模式读取的非易失性存储器件和相应的读取方法
公开(公告)号：US06854040B1
公开(公告)日：2005-02-08
申请号：US09717938
申请日：2000-11-21
申请人： Simone Bartoli , Antonino Geraci , Mauro Sali , Lorenzo Bedarida
发明人： Simone Bartoli , Antonino Geraci , Mauro Sali , Lorenzo Bedarida
IPC分类号： G11C7/10 , G06F12/00 , G06F13/28 , G11C8/04
CPC分类号： G11C7/1072 , G11C7/1033 , G11C7/1045
摘要： A read control circuit and a reading method for an electronic memory device integrated on a semiconductor includes a non-volatile memory matrix with associated row and column decoders connected to respective outputs of an address counter. An address transition detect (ATD) circuit detects an input transition as the memory device is being accessed, and read amplifiers and attendant registers transfer the data read from the memory matrix to the output. The read control circuit includes a detection circuit to which is input a clock signal and a logic signal to enable reading in the burst mode. A burst read mode control logic circuit is connected downstream of the detection circuit. The method includes accessing the memory matrix in a random read mode, detecting a request for access in the burst read mode, and executing the parallel reading of a plurality of memory words during a single period of time clocked by the clock signal.
摘要翻译：集成在半导体上的电子存储装置的读取控制电路和读取方法包括具有连接到地址计数器的相应输出的相关联的行和列解码器的非易失性存储器矩阵。地址转换检测（ATD）电路在正在访问存储器件时检测输入转换，并且读取放大器和伴随寄存器将从存储器矩阵读取的数据传送到输出。读取控制电路包括检测电路，在该检测电路中输入时钟信号和逻辑信号，使得能够以突发模式进行读取。突发读模式控制逻辑电路连接在检测电路的下游。该方法包括以随机读取模式访问存储器矩阵，以突发读取模式检测访问请求，以及在由时钟信号计时的单个时间段内执行多个存储器字的并行读取。

40. 发明授权

US06401164B1 Sectored semiconductor memory device with configurable memory sector addresses 有权
标题翻译：具有可配置存储器扇区地址的扇区半导体存储器件
公开(公告)号：US06401164B1
公开(公告)日：2002-06-04
申请号：US09159322
申请日：1998-09-23
申请人： Simone Bartoli , Vincenzo Dima , Mauro Luigi Sali
发明人： Simone Bartoli , Vincenzo Dima , Mauro Luigi Sali
IPC分类号： G06F1206
CPC分类号： G11C8/12 , G11C16/08
摘要： A memory device comprises a plurality of independent memory sectors, external address signal inputs for receiving external address signals that address individual memory locations of the memory device, the external address signals including external memory sector address signals allowing for individually addressing each memory sector, and a memory sector selection circuit for selecting one of the plurality of memory sectors according to a value of the external memory sector address signals. A first and a second alternative internal memory sector address signal paths are provided for supplying the external memory sector address signals to the memory sector selection circuit, the first path providing no logic inversion and the second path providing logic inversion. A programmable circuit activates either one or the other of the first and second internal memory sector address signal paths, so that a position of each memory sector in a space of values (00000h-3FFFFh) of the external address signals can be changed by activating either one or the other of the first and second internal memory sector address signal paths.
摘要翻译：存储器件包括多个独立存储器扇区，外部地址信号输入用于接收寻址存储器件的各个存储器位置的外部地址信号，外部地址信号包括允许单独寻址每个存储器扇区的外部存储器扇区地址信号，以及存储器扇区选择电路，用于根据外部存储器扇区地址信号的值来选择多个存储器扇区之一。提供第一和第二替代的内部存储器扇区地址信号路径用于将外部存储器扇区地址信号提供给存储器扇区选择电路，第一路径不提供逻辑反转，而第二路径提供逻辑反转。可编程电路激活第一和第二内部存储器扇区地址信号路径中的一个或另一个，使得外部地址信号的值（00000h-3FFFFh）的空间中的每个存储器扇区的位置可以通过激活第一和第二内部存储器扇区地址信号路径中的一个或另一个。

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