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31. 发明授权

US08133067B2 Electrical connector with locking engagement between an actuator and an insulative housing 有权
标题翻译：电连接器，其具有致动器和绝缘壳体之间的锁定接合
公开(公告)号：US08133067B2
公开(公告)日：2012-03-13
申请号：US12778963
申请日：2010-05-12
申请人： Tzu-Ching Tsai , Xiao-Dong Wang
发明人： Tzu-Ching Tsai , Xiao-Dong Wang
IPC分类号： H01R13/15
CPC分类号： H01R12/79 , H01R12/88
摘要： An electrical connector for connecting a flexible printed circuit board comprises an insulator, a plurality of terminals and an actuator mounting onto the insulator. The insulator comprises a top wall, a bottom wall opposite to the top wall and a pair of side wall joining with the top wall and the bottom wall thereby defining a cavity therebetween. The terminals arranged exposed into the cavity. The actuator can rotate between an opened position where the flexible printed circuit board can be inserted into the cavity and a closed position where the flexible printed circuit board can be abutted against the terminals. A post protrudes from the bottom wall. The actuator defines a locking beam for locking with the post and a through hole for receiving the post when the actuator is located at the closed position.
摘要翻译：用于连接柔性印刷电路板的电连接器包括绝缘体，多个端子和安装在绝缘体上的致动器。绝缘体包括顶壁，与顶壁相对的底壁和与顶壁和底壁接合的一对侧壁，从而在其间限定空腔。端子布置成暴露在空腔中。致动器可以在柔性印刷电路板可以插入空腔的打开位置和柔性印刷电路板可以抵靠端子的关闭位置之间旋转。柱从底壁突出。致动器限定了用于与柱一起锁定的锁定梁和当致动器位于关闭位置时用于接收柱的通孔。

32. 发明授权

US07892035B2 Electrical card connector with moveable housing 有权
标题翻译：带移动外壳的电子卡连接器
公开(公告)号：US07892035B2
公开(公告)日：2011-02-22
申请号：US12542714
申请日：2009-08-18
申请人： Tzu-Ching Tsai , Kuo-Chun Hsu
发明人： Tzu-Ching Tsai , Kuo-Chun Hsu
IPC分类号： H01R24/00
CPC分类号： H01R12/714 , H01R12/721 , H01R13/6594 , H01R27/02 , Y10S439/946
摘要： An electrical card connector includes a first insulative housing (1), a number of first contacts (2) mounted in the first housing and having a first soldering portion (22), a second insulative housing (4) located behind the first housing, a number of second contacts (5) mounted in the second housing and having a second soldering portion (51), and a shell (6) covering the first housing and the second housing. The first housing and the second housing is separated each other. A gap (9) is formed between the shell and the second housing. The second housing with the second contacts moves around the gap, corresponding to the first housing, and then the second soldering portion is adjusted, the first soldering portion and the second soldering portion are in coplanar, and soldered on the PCB without missing.
摘要翻译：电卡连接器包括第一绝缘壳体（1），安装在第一壳体中并具有第一焊接部分（22）的多个第一触头（2），位于第一壳体后面的第二绝缘壳体（4）安装在第二壳体中并具有第二焊接部分（51）的第二触点（5）的数量，以及覆盖第一壳体和第二壳体的壳体（6）。第一壳体和第二壳体彼此分离。在壳体和第二壳体之间形成间隙（9）。具有第二触头的第二壳体围绕第一壳体的间隙移动，然后调整第二焊接部分，第一焊接部分和第二焊接部分共面，并且焊接在PCB上而不丢失。

33. 外观设计

USD587209S1 Electrical connector 有权
公开(公告)号：USD587209S1
公开(公告)日：2009-02-24
申请号：US29308722
申请日：2008-07-01
申请人： Tzu-Ching Tsai , Ren-Chih Li
设计人： Tzu-Ching Tsai , Ren-Chih Li

34. 发明授权

US06977134B2 Manufacturing method of a MOSFET gate 有权
标题翻译： MOSFET栅极的制造方法
公开(公告)号：US06977134B2
公开(公告)日：2005-12-20
申请号：US10452274
申请日：2003-06-02
申请人： Chung-Peng Hao , Hui-Min Mao , Yi-Nan Chen , Tzu-Ching Tsai
发明人： Chung-Peng Hao , Hui-Min Mao , Yi-Nan Chen , Tzu-Ching Tsai
IPC分类号： H01L21/336 , G03C5/00
CPC分类号： H01L29/66583
摘要： A manufacturing method for a MOSFET gate structure. The method comprises providing a substrate, sequentially depositing a pad layer and a dielectric layer thereon, defining a gate trench passing through the dielectric layer and the pad layer to expose a predetermined gate area of the substrate, sequentially forming a gate dielectric layer, a first conductive layer, a second conductive layer, and a cap layer on the exposed substrate in the gate trench to form a damascene gate structure, and removing the dielectric layer.
摘要翻译：一种用于MOSFET栅极结构的制造方法。该方法包括提供衬底，在其上依次沉积衬垫层和电介质层，限定通过介电层和焊盘层的栅极沟槽，以暴露衬底的预定栅极区域，顺序地形成栅极电介质层，第一导电层，第二导电层和盖层，以形成镶嵌栅极结构，并去除介电层。

35. 发明授权

US06838866B2 Process for measuring depth of source and drain 有权
标题翻译：测量源和漏源深度的过程
公开(公告)号：US06838866B2
公开(公告)日：2005-01-04
申请号：US10283699
申请日：2002-10-30
申请人： Tzu-Ching Tsai , Hui Min Mao
发明人： Tzu-Ching Tsai , Hui Min Mao
IPC分类号： H01L21/334 , H01L21/66 , H01L21/762 , H01L21/8242 , H01L23/544 , H01L27/108 , G01R31/26
CPC分类号： H01L22/34 , H01L21/76224 , H01L22/12 , H01L27/10829 , H01L27/10867 , H01L27/1087 , H01L29/66181
摘要： A process for measuring depth of a source and drain of a MOS transistor. The MOS transistor is formed on a semiconductor substrate on which a trench capacitor is formed and a buried strap is formed between the MOS transistor and the trench capacitor. The process includes the following steps. First, resistances of the buried strap at a plurality of different depths are measured. Next, a curve correlating the resistances with the depths is established. Next, slopes of the resistance to the depth for the curve are obtained. Finally, a depth corresponding to a minimum resistance before the slope of the resistance to the depth reaches to zero is obtained.
摘要翻译：用于测量MOS晶体管的源极和漏极的深度的过程。 MOS晶体管形成在其上形成有沟槽电容器的半导体衬底上，并且在MOS晶体管和沟槽电容器之间形成掩埋带。该过程包括以下步骤。首先，测量在多个不同深度处的掩埋带的电阻。接下来，建立将电阻与深度相关联的曲线。接下来，获得对曲线的深度的阻力的斜率。最后，获得与深度电阻斜率之前的最小电阻对应的深度达到零的深度。

36. 发明授权

US06790740B2 Process for filling polysilicon seam 有权
标题翻译：填充多晶硅缝的工艺
公开(公告)号：US06790740B2
公开(公告)日：2004-09-14
申请号：US10375485
申请日：2003-02-27
申请人： Tse-Yao Huang , Tzu-Ching Tsai , Yi-Nan Chen
发明人： Tse-Yao Huang , Tzu-Ching Tsai , Yi-Nan Chen
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L29/66181
摘要： A process for filling a polysilicon seam. First, a semiconducting substrate or an insulating layer having a trench is provided, and a first polysilicon layer having a seam is filled in the trench. Next, the first polysilicon layer is etched to expose the seam. Next, a second polysilicon layer is formed to fill the top portion of the seam and close the seam.
摘要翻译：一种填充多晶硅接缝的工艺。首先，提供具有沟槽的半导体衬底或绝缘层，并且在沟槽中填充具有接缝的第一多晶硅层。接下来，蚀刻第一多晶硅层以暴露接缝。接下来，形成第二多晶硅层以填充接缝的顶部并闭合接缝。

37. 发明授权

US06750147B2 Process for integration of a trench for capacitors and removal of black silicon 有权
标题翻译：用于集成电容器沟槽和去除黑色硅的工艺
公开(公告)号：US06750147B2
公开(公告)日：2004-06-15
申请号：US10193482
申请日：2002-07-10
申请人： Tzu-Ching Tsai , Frasier Wang
发明人： Tzu-Ching Tsai , Frasier Wang
IPC分类号： H01L21302
CPC分类号： H01L21/02043 , H01L27/1087 , H01L27/10894
摘要： A process for integration of a trench for capacitors and removal of black silicon. A semiconductor substrate is etched to form a capacitor trench having a predetermined depth, and black silicon spikes are generated on the semiconductor substrate at the edge region. A thermal oxide film is grown conformally on the capacitor trench. A sacrificial layer is then formed on the semiconductor substrate at the memory cell region, wherein the sacrificial layer is filled into the capacitor trench. The black silicon spikes are removed while the sacrificial layer is used as the shield. The sacrificial layer is partially removed to expose the thermal oxide film. The exposed thermal oxide film is then removed. Finally, the residual sacrificial structure is removed.
摘要翻译：用于集成电容器沟槽和去除黑色硅的工艺。蚀刻半导体衬底以形成具有预定深度的电容器沟槽，并且在边缘区域处在半导体衬底上产生黑色硅尖峰。在电容器沟槽上保形地生长热氧化膜。然后在存储单元区域的半导体衬底上形成牺牲层，其中牺牲层被填充到电容器沟槽中。当牺牲层用作屏蔽时，去除黑色硅尖峰。牺牲层被部分去除以暴露热氧化膜。然后去除暴露的热氧化膜。最后，去除残留的牺牲结构。

38. 发明授权

US06703311B2 Method for estimating capacitance of deep trench capacitors 有权
标题翻译：深沟槽电容器电容估算方法
公开(公告)号：US06703311B2
公开(公告)日：2004-03-09
申请号：US10163240
申请日：2002-06-04
申请人： Tzu-Ching Tsai , Hui Min Mao , Ying Huan Chuang , Yu-Pi Lee
发明人： Tzu-Ching Tsai , Hui Min Mao , Ying Huan Chuang , Yu-Pi Lee
IPC分类号： H01L21302
CPC分类号： H01L27/10861 , G01R31/275 , H01L22/34
摘要： A method for estimating capacitance of deep trench capacitor in a substrate. After a photoresist layer used to define the region of the lower electrode is formed on an oxide layer doping with a conducting type dopant, the height difference of the photoresist layer between the memory cell array area and the supporting area is measured. The radicand of the height difference is directly proportional to a capacitance of a capacitor to-be-formed in the trenches.
摘要翻译：一种用于估计衬底中的深沟槽电容器的电容的方法。在用于限定下电极的区域的光致抗蚀剂层形成在掺杂有导电型掺杂剂的氧化物层上之后，测量存储单元阵列区域和支撑区域之间的光致抗蚀剂层的高度差。高度差的根数与沟槽中要形成的电容器的电容成正比。

39. 发明授权

US06610567B2 DRAM having a guard ring and process of fabricating the same 有权
公开(公告)号：US06610567B2
公开(公告)日：2003-08-26
申请号：US10136656
申请日：2002-04-30
申请人： I-Sheng Liu , Tzu-Ching Tsai
发明人： I-Sheng Liu , Tzu-Ching Tsai
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/1087 , H01L29/945
摘要： A DRAM having a guard ring comprises a semiconductor substrate having a memory array area and a guard ring area; a first trench disposed on said memory array area; a second trench disposed on said guard ring area; a first doped strap disposed on the upper surface of said semiconductor substrate around said first trench; a second doped strap disposed on the upper surface of said semiconductor substrate around said second trench. Furthermore, the DRAM comprises a first doped plate disposed on said semiconductor substrate around the bottom of said first trench, and is separated from said first doped strap by a predetermined distance; and a second doped plate disposed on said semiconductor substrate around the bottom of said second trench, and is connected to said second doped strap.

40. 发明授权

US06407421B1 DRAM having a guard ring and process of fabricating the same 有权
标题翻译：具有保护环的DRAM及其制造方法
公开(公告)号：US06407421B1
公开(公告)日：2002-06-18
申请号：US09658685
申请日：2000-09-08
申请人： Sheng M. Liu , Tzu-Ching Tsai
发明人： Sheng M. Liu , Tzu-Ching Tsai
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L27/1087 , H01L29/945
摘要： A DRAM having a guard ring comprises a semiconductor substrate having a memory array area and a guard ring area; a first trench disposed on said memory array area; a second trench disposed on said guard ring area; a first doped strap disposed on the upper surface of said semiconductor substrate around said first trench; a second doped strap disposed on the upper surface of said semiconductor substrate around said second trench. Furthermore, the DRAM comprises a first doped plate disposed on said semiconductor substrate around the bottom of said first trench, and is separated from said first doped strap by a predetermined distance; and a second doped plate disposed on said semiconductor substrate around the bottom of said second trench, and is connected to said second doped strap.
摘要翻译：具有保护环的DRAM包括具有存储器阵列区域和保护环区域的半导体衬底; 设置在所述存储器阵列区域上的第一沟槽; 设置在所述保护环区域上的第二沟槽; 第一掺杂带，设置在所述半导体衬底的围绕所述第一沟槽的上表面上; 第二掺杂带，设置在所述半导体衬底的围绕所述第二沟槽的上表面上。此外，DRAM包括设置在所述半导体衬底周围所述第一沟槽的底部的第一掺杂板，并且与所述第一掺杂带隔开预定距离; 以及第二掺杂板，设置在所述第二沟槽的底部周围的所述半导体衬底上，并且连接到所述第二掺杂带。

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