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1. 发明授权

US06964926B2 Method of forming geometric deep trench capacitors 有权
标题翻译：形成几何深沟槽电容器的方法
公开(公告)号：US06964926B2
公开(公告)日：2005-11-15
申请号：US10727924
申请日：2003-12-04
申请人： Tse-Yao Huang , Yi-Nan Chen , Tzu-Ching Tsai
发明人： Tse-Yao Huang , Yi-Nan Chen , Tzu-Ching Tsai
IPC分类号： H01L21/20 , H01L21/308 , H01L21/334 , H01L21/762 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181 , Y10S438/942
摘要： A method of forming capacitors with geometric deep trenches. First, a substrate with a pad structure formed thereon is provided, and a first hard mask layer is formed on the pad structure. Next, a second hard mask layer is formed on the first hard mask layer. Next, a spacer layer is formed in the first opening on the first hard mask layer to expose a second opening. Next, a third hard mask layer is filled the second opening, and the spacer layer is removed. Next, the first hard mask layer is etched to expose a third opening with a salient of the first hard mask layer, with the second hard mask layer and the third hard mask layer acting as masks. Finally, the first hard mask layer, the pad structure, and the substrate are etched to form a geometric deep trench.
摘要翻译：一种形成具有几何深沟槽的电容器的方法。首先，提供在其上形成有衬垫结构的衬底，并且在衬垫结构上形成第一硬掩模层。接着，在第一硬掩模层上形成第二硬掩模层。接下来，在第一硬掩模层上的第一开口中形成间隔层以露出第二开口。接下来，在第二开口填充第三硬掩模层，并且移除间隔层。接下来，第一硬掩模层被蚀刻以暴露具有第一硬掩模层的凸起的第三开口，第二硬掩模层和第三硬掩模层用作掩模。最后，蚀刻第一硬掩模层，焊盘结构和衬底以形成几何深沟槽。

2. 发明授权

US07807558B2 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07807558B2
公开(公告)日：2010-10-05
申请号：US11933732
申请日：2007-11-01
申请人： Tzu-Ching Tsai , Tse-Yao Huang , Yi-Nan Chen
发明人： Tzu-Ching Tsai , Tse-Yao Huang , Yi-Nan Chen
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/02063 , H01L21/02071 , H01L21/32137
摘要： A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises providing a substrate. Next, an insulating layer, a conductive layer and a silicide layer are formed on the substrate in sequence. Next, a hard masking layer is formed on the silicide layer exposing a portion of the silicide layer. A first etching step is performed to remove the silicide layer and the underlying conductive layer which are not covered by the hard masking layer, thereby forming a gate stack. And next, a second etching step is performed to remove any remaining conductive layer not covered by the hard masking layer after the first etching step. The second etching step is performed with an etchant comprising ammonium hydroxide.
摘要翻译：提供一种制造半导体器件的方法。制造半导体器件的方法包括提供衬底。接下来，依次在基板上形成绝缘层，导电层和硅化物层。接下来，在暴露硅化物层的一部分的硅化物层上形成硬掩模层。执行第一蚀刻步骤以去除未被硬掩模层覆盖的硅化物层和下面的导电层，从而形成栅极堆叠。接下来，执行第二蚀刻步骤以在第一蚀刻步骤之后去除未被硬掩模层覆盖的剩余导电层。用包含氢氧化铵的蚀刻剂进行第二蚀刻步骤。

3. 发明授权

US06790740B2 Process for filling polysilicon seam 有权
标题翻译：填充多晶硅缝的工艺
公开(公告)号：US06790740B2
公开(公告)日：2004-09-14
申请号：US10375485
申请日：2003-02-27
申请人： Tse-Yao Huang , Tzu-Ching Tsai , Yi-Nan Chen
发明人： Tse-Yao Huang , Tzu-Ching Tsai , Yi-Nan Chen
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L29/66181
摘要： A process for filling a polysilicon seam. First, a semiconducting substrate or an insulating layer having a trench is provided, and a first polysilicon layer having a seam is filled in the trench. Next, the first polysilicon layer is etched to expose the seam. Next, a second polysilicon layer is formed to fill the top portion of the seam and close the seam.
摘要翻译：一种填充多晶硅接缝的工艺。首先，提供具有沟槽的半导体衬底或绝缘层，并且在沟槽中填充具有接缝的第一多晶硅层。接下来，蚀刻第一多晶硅层以暴露接缝。接下来，形成第二多晶硅层以填充接缝的顶部并闭合接缝。

4. 发明授权

US08963282B2 Crack stop structure and method for forming the same 有权
标题翻译：断裂结构及其形成方法
公开(公告)号：US08963282B2
公开(公告)日：2015-02-24
申请号：US13231961
申请日：2011-09-14
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/72 , H01L23/31 , H01L23/00 , H01L21/78 , H01L21/56
CPC分类号： H01L23/562 , H01L21/311 , H01L21/561 , H01L21/76224 , H01L21/78 , H01L23/3178 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.
摘要翻译：半导体结构包括矩阵，集成电路和划线。矩阵包括划线区域和电路区域。集成电路设置在电路区域内。划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

5. 发明授权

US08692245B2 Crack stop structure and method for forming the same 有权
标题翻译：断裂结构及其形成方法
公开(公告)号：US08692245B2
公开(公告)日：2014-04-08
申请号：US13214227
申请日：2011-08-21
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/544 , H01L23/482 , H01L21/762
CPC分类号： H01L21/76224 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.
摘要翻译：本发明在第一方面提出了一种具有裂纹停止结构的半导体结构。半导体结构包括矩阵，集成电路和划线。矩阵包括划线区域和电路区域。集成电路设置在电路区域内。划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

6. 发明申请

US20130062727A1 CRACK STOP STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：裂缝停止结构及其形成方法
公开(公告)号：US20130062727A1
公开(公告)日：2013-03-14
申请号：US13231961
申请日：2011-09-14
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L23/562 , H01L21/311 , H01L21/561 , H01L21/76224 , H01L21/78 , H01L23/3178 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.
摘要翻译：半导体结构包括矩阵，集成电路和划线。矩阵包括划线区域和电路区域。集成电路设置在电路区域内。划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

7. 发明授权

US06992393B2 Interconnect structure and method for fabricating the same 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US06992393B2
公开(公告)日：2006-01-31
申请号：US10708848
申请日：2004-03-29
申请人： Tse-Yao Huang , Yi-Nan Chen , Chih-Ching Lin
发明人： Tse-Yao Huang , Yi-Nan Chen , Chih-Ching Lin
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/7685 , H01L21/76802 , H01L21/76832 , H01L21/76837
摘要： A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.
摘要翻译：提供一种用于制造互连的方法。该方法包括在第一电介质层上形成导线; 在所述第一介电层和所述导电线的表面上形成第一衬里层; 在所述第一衬里层上形成第二衬里层; 在所述第二衬里层上形成第二电介质层，其中所述第二电介质层的蚀刻选择率高于所述第二衬垫的蚀刻选择率; 以及图案化所述第二电介质层以形成穿过所述第二衬垫层和所述第一衬里层的接触窗口，以露出所述导电线的表面。由于第二电介质层的蚀刻速率高于第二衬垫层的蚀刻速率，所以第二衬里层可以用作蚀刻停止层，同时构图第二介电层。

8. 发明授权

US06908840B2 Method of filling bit line contact via 有权
标题翻译：填充位线接触的方法
公开(公告)号：US06908840B2
公开(公告)日：2005-06-21
申请号：US10640096
申请日：2003-08-13
申请人： Tse-Yao Huang , Yi-Nan Chen
发明人： Tse-Yao Huang , Yi-Nan Chen
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8242 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76834 , H01L21/76847 , H01L27/10873 , H01L27/10888
摘要： A method of filling a bit line contact via. The method includes providing a substrate having a transistor, with a gate electrode, drain region, and source region, on the substrate, forming a first barrier layer overlying the sidewall of the gate electrode, drain region, and source region, forming a first conductive layer overlying the first barrier layer, removing the first barrier layer and first conductive layer above the source region, forming an insulating barrier layer overlying the substrate, forming a first dielectric layer overlying the insulating barrier layer above the source region, forming a second dielectric layer overlying the substrate, forming a via through the second dielectric layer and the insulative barrier layer, exposing the first conductive layer, forming a second barrier layer overlying the surface of the via, and filling the via with a second conductive layer.
摘要翻译：填充位线接触通孔的方法。该方法包括在衬底上提供具有栅电极，漏极区和源极区的晶体管的衬底，形成覆盖在栅电极，漏区和源极区的侧壁上的第一势垒层，形成第一导电层，覆盖第一阻挡层，去除源极区上方的第一阻挡层和第一导电层，形成覆盖在衬底上的绝缘阻挡层，形成覆盖在源区上方的绝缘阻挡层的第一介电层，形成第二介电层覆盖衬底，通过第二电介质层和绝缘阻挡层形成通孔，暴露第一导电层，形成覆盖通孔表面的第二阻挡层，并用第二导电层填充通孔。

9. 发明授权

US07094638B2 Method of forming gate structure 有权
标题翻译：形成栅极结构的方法
公开(公告)号：US07094638B2
公开(公告)日：2006-08-22
申请号：US10605678
申请日：2003-10-17
申请人： Jin-Tau Huang , Chung-Peng Hao , Yi-Nan Chen , Tse-Yao Huang
发明人： Jin-Tau Huang , Chung-Peng Hao , Yi-Nan Chen , Tse-Yao Huang
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/28247 , H01L21/28061
摘要： A method of forming a gate structure. First, a substrate is provided, and a gate oxide layer, a polysilicon layer, a silicide layer, and a cap layer are consecutively formed onto the substrate. Then, an etching process is performed to etch a portion of the cap layer, the silicide layer, and the polysilicon layer and stop on the polysilicon layer for forming a stacked gate. Thereafter, a portion of the silicide layer exposed on sidewalls of the stacked gate is removed to form a recess. A passivation layer is deposited to fill the recess. The remaining polysilicon layer and the gate oxide layer outside the sidewalls of the stacked gate structure are removed.
摘要翻译：一种形成栅极结构的方法。首先，提供基板，并且在基板上连续地形成栅氧化层，多晶硅层，硅化物层和盖层。然后，进行蚀刻处理以蚀刻覆盖层，硅化物层和多晶硅层的一部分，并停留在多晶硅层上以形成堆叠栅极。此后，去除暴露在堆叠栅极的侧壁上的硅化物层的一部分以形成凹陷。沉积钝化层以填充凹部。除去堆叠栅结构的侧壁外的剩余多晶硅层和栅氧化层。

10. 发明授权

US07052949B2 Method for forming bit line 有权
标题翻译：位线形成方法
公开(公告)号：US07052949B2
公开(公告)日：2006-05-30
申请号：US10459327
申请日：2003-06-11
申请人： Kuo-Chien Wu , Tse-Yao Huang , Yi-Nan Chen
发明人： Kuo-Chien Wu , Tse-Yao Huang , Yi-Nan Chen
IPC分类号： H01L21/4763 , H01L21/8238
CPC分类号： H01L21/76802 , H01L27/10888 , H01L27/10894
摘要： A method for forming a bit line. A semiconductor substrate is provided. A MOS having a gate and an S/D area is formed on the semiconductor substrate. A first dielectric layer with a first opening is formed on the semiconductor substrate to expose the S/D area. A conducting layer is formed in the first opening. A barrier layer is formed on the surface of the first dielectric layer and the conducting layer. A second dielectric layer having a second opening and a third opening is formed on the barrier layer, the position of the second opening corresponding to the first opening. Metal layers are formed in the second opening and the third opening as bit lines, respectively.
摘要翻译：一种形成位线的方法。提供半导体衬底。在半导体衬底上形成具有栅极和S / D区域的MOS。在半导体衬底上形成具有第一开口的第一电介质层，以暴露S / D区域。在第一开口中形成导电层。在第一电介质层和导电层的表面上形成阻挡层。具有第二开口和第三开口的第二电介质层形成在阻挡层上，第二开口的位置对应于第一开口。分别在第二开口和第三开口中形成金属层作为位线。

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