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1. 发明申请

US20060118886A1 Method of forming bit line contact via 审中-公开
标题翻译：形成位线接触通孔的方法
公开(公告)号：US20060118886A1
公开(公告)日：2006-06-08
申请号：US11338330
申请日：2006-01-23
申请人： Tzu-Ching Tsai , Yi-Nan Chen , Hui-Min Mao
发明人： Tzu-Ching Tsai , Yi-Nan Chen , Hui-Min Mao
IPC分类号： H01L29/772
CPC分类号： H01L21/76897 , H01L21/76829 , H01L21/76895
摘要： A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.
摘要翻译：形成位线接触通孔的方法。该方法包括提供具有晶体管的衬底，该晶体管具有栅极，漏极区和源极区，形成覆盖漏极区的导电层，保形地形成覆盖衬底的绝缘阻挡层，覆盖在绝缘阻挡层上的绝缘层并且通过介电层和绝缘阻挡层形成通孔，暴露导电层。

2. 发明授权

US07195975B2 Method of forming bit line contact via 有权
标题翻译：形成位线接触通孔的方法
公开(公告)号：US07195975B2
公开(公告)日：2007-03-27
申请号：US10714001
申请日：2003-11-14
申请人： Tzu-Ching Tsai , Yi-Nan Chen , Hui-Min Mao
发明人： Tzu-Ching Tsai , Yi-Nan Chen , Hui-Min Mao
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L21/76897 , H01L21/76829 , H01L21/76895
摘要： A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.
摘要翻译：形成位线接触通孔的方法。该方法包括提供具有晶体管的衬底，该晶体管具有栅极，漏极区和源极区，形成覆盖漏极区的导电层，保形地形成覆盖衬底的绝缘阻挡层，覆盖在绝缘阻挡层上的绝缘层并且通过介电层和绝缘阻挡层形成通孔，暴露导电层。

3. 发明授权

US06709975B2 Method of forming inter-metal dielectric 有权
标题翻译：形成金属间电介质的方法
公开(公告)号：US06709975B2
公开(公告)日：2004-03-23
申请号：US10222349
申请日：2002-08-16
申请人： Hui Min Mao , Yi-Nan Chen , Tzu-Ching Tsai
发明人： Hui Min Mao , Yi-Nan Chen , Tzu-Ching Tsai
IPC分类号： H01L214763
CPC分类号： H01L21/76837 , H01L21/76885
摘要： A method of forming inter-metal dielectric (IMD). A substrate having a patterned metal layer thereon has at least one opening to expose the substrate. The opening has an aspect ratio of 3.5˜4.5. Next, the opening is filled with a first dielectric layer, and voids are formed in the upper portion of the first dielectric layer due to the high aspect ratio opening. Thereafter, the first dielectric layer is etched to leave the first dielectric layer with a predetermined height in the opening without voids. Finally, a second dielectric layer is formed on the first dielectric layer to completely fill the opening.
摘要翻译：一种形成金属间电介质（IMD）的方法。其上具有图案化金属层的衬底具有至少一个露出衬底的开口。开口的长宽比为3.5〜4.5。接下来，开口填充有第一电介质层，并且由于高纵横比开口，在第一电介质层的上部形成空隙。此后，蚀刻第一电介质层以使第一介电层在开口中具有预定的高度而没有空隙。最后，在第一电介质层上形成第二电介质层以完全填充开口。

4. 发明授权

US06706587B1 Method for forming buried plates 有权
标题翻译：掩埋板成型方法
公开(公告)号：US06706587B1
公开(公告)日：2004-03-16
申请号：US10406371
申请日：2003-04-03
申请人： Tzu-Ching Tsai , Hui Min Mao , Ying Huan Chuang
发明人： Tzu-Ching Tsai , Hui Min Mao , Ying Huan Chuang
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L28/84 , H01L29/66181
摘要： Method for forming buried plates. The method includes providing a substrate formed with a pad stacked layer on the surface, a bottle trench and a protective layer on the upper sidewalls of the bottle trench, forming a doped hemispherical silicon grain (HSG) layer on the protective layer and the sidewalls and bottom of the bottle trench, removing the hemispherical silicon grain layer on the protective layer without removing the hemispherical silicon grain layer from the lower sidewalls and bottom of the bottle trench, forming a covering layer on the protective layer, and subjecting the doped hemispherical silicon grain layer to drive-in annealing so that ions in the HSG layer diffuse out to the substrate, thereby forming a buried plate within the lower sidewalls of the bottle trench.
摘要翻译：掩埋板成型方法该方法包括提供在表面上形成有垫堆叠层的基底，瓶沟槽和瓶沟槽的上侧壁上的保护层，在保护层和侧壁上形成掺杂半球形硅晶粒（HSG）层，以及在瓶子沟槽的底部，去除保护层上的半球形硅晶粒层，而不从瓶沟槽的下侧壁和底部移除半球状硅晶粒层，在保护层上形成覆盖层，并对掺杂的半球形硅颗粒层以驱动退火，使得HSG层中的离子扩散到衬底，从而在瓶沟槽的下侧壁内形成掩埋板。

5. 发明授权

US06977134B2 Manufacturing method of a MOSFET gate 有权
标题翻译： MOSFET栅极的制造方法
公开(公告)号：US06977134B2
公开(公告)日：2005-12-20
申请号：US10452274
申请日：2003-06-02
申请人： Chung-Peng Hao , Hui-Min Mao , Yi-Nan Chen , Tzu-Ching Tsai
发明人： Chung-Peng Hao , Hui-Min Mao , Yi-Nan Chen , Tzu-Ching Tsai
IPC分类号： H01L21/336 , G03C5/00
CPC分类号： H01L29/66583
摘要： A manufacturing method for a MOSFET gate structure. The method comprises providing a substrate, sequentially depositing a pad layer and a dielectric layer thereon, defining a gate trench passing through the dielectric layer and the pad layer to expose a predetermined gate area of the substrate, sequentially forming a gate dielectric layer, a first conductive layer, a second conductive layer, and a cap layer on the exposed substrate in the gate trench to form a damascene gate structure, and removing the dielectric layer.
摘要翻译：一种用于MOSFET栅极结构的制造方法。该方法包括提供衬底，在其上依次沉积衬垫层和电介质层，限定通过介电层和焊盘层的栅极沟槽，以暴露衬底的预定栅极区域，顺序地形成栅极电介质层，第一导电层，第二导电层和盖层，以形成镶嵌栅极结构，并去除介电层。

6. 发明授权

US06838866B2 Process for measuring depth of source and drain 有权
标题翻译：测量源和漏源深度的过程
公开(公告)号：US06838866B2
公开(公告)日：2005-01-04
申请号：US10283699
申请日：2002-10-30
申请人： Tzu-Ching Tsai , Hui Min Mao
发明人： Tzu-Ching Tsai , Hui Min Mao
IPC分类号： H01L21/334 , H01L21/66 , H01L21/762 , H01L21/8242 , H01L23/544 , H01L27/108 , G01R31/26
CPC分类号： H01L22/34 , H01L21/76224 , H01L22/12 , H01L27/10829 , H01L27/10867 , H01L27/1087 , H01L29/66181
摘要： A process for measuring depth of a source and drain of a MOS transistor. The MOS transistor is formed on a semiconductor substrate on which a trench capacitor is formed and a buried strap is formed between the MOS transistor and the trench capacitor. The process includes the following steps. First, resistances of the buried strap at a plurality of different depths are measured. Next, a curve correlating the resistances with the depths is established. Next, slopes of the resistance to the depth for the curve are obtained. Finally, a depth corresponding to a minimum resistance before the slope of the resistance to the depth reaches to zero is obtained.
摘要翻译：用于测量MOS晶体管的源极和漏极的深度的过程。 MOS晶体管形成在其上形成有沟槽电容器的半导体衬底上，并且在MOS晶体管和沟槽电容器之间形成掩埋带。该过程包括以下步骤。首先，测量在多个不同深度处的掩埋带的电阻。接下来，建立将电阻与深度相关联的曲线。接下来，获得对曲线的深度的阻力的斜率。最后，获得与深度电阻斜率之前的最小电阻对应的深度达到零的深度。

7. 发明授权

US06703311B2 Method for estimating capacitance of deep trench capacitors 有权
标题翻译：深沟槽电容器电容估算方法
公开(公告)号：US06703311B2
公开(公告)日：2004-03-09
申请号：US10163240
申请日：2002-06-04
申请人： Tzu-Ching Tsai , Hui Min Mao , Ying Huan Chuang , Yu-Pi Lee
发明人： Tzu-Ching Tsai , Hui Min Mao , Ying Huan Chuang , Yu-Pi Lee
IPC分类号： H01L21302
CPC分类号： H01L27/10861 , G01R31/275 , H01L22/34
摘要： A method for estimating capacitance of deep trench capacitor in a substrate. After a photoresist layer used to define the region of the lower electrode is formed on an oxide layer doping with a conducting type dopant, the height difference of the photoresist layer between the memory cell array area and the supporting area is measured. The radicand of the height difference is directly proportional to a capacitance of a capacitor to-be-formed in the trenches.
摘要翻译：一种用于估计衬底中的深沟槽电容器的电容的方法。在用于限定下电极的区域的光致抗蚀剂层形成在掺杂有导电型掺杂剂的氧化物层上之后，测量存储单元阵列区域和支撑区域之间的光致抗蚀剂层的高度差。高度差的根数与沟槽中要形成的电容器的电容成正比。

8. 发明授权

US07982315B2 Semiconductor structure and method of making the same 有权
标题翻译：半导体结构及制作方法
公开(公告)号：US07982315B2
公开(公告)日：2011-07-19
申请号：US12165587
申请日：2008-06-30
申请人： Yinan Chen , Hsien-Wen Liu , Tzu-Ching Tsai
发明人： Yinan Chen , Hsien-Wen Liu , Tzu-Ching Tsai
IPC分类号： H01L23/48
CPC分类号： H01L23/53295 , H01L21/76831 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided. An amorphous silicon layer that acts as a UV blocking layer replaces a conventional silicon-rich oxide (SRO) layer or the super silicon-rich oxide (SSRO) layer. By doing this, the process window is increased. In addition, silicon nitride sidewall spacer is formed inside the contact hole to prevent charge loss.
摘要翻译：提供半导体器件。作为UV阻挡层的非晶硅层代替常规富硅氧化物（SRO）层或超富硅氧化物（SSRO）层。通过这样做，过程窗口增加。此外，在接触孔内部形成氮化硅侧壁间隔物，以防止电荷损失。

9. 发明授权

US07878858B1 N-in-1 card connector 有权
标题翻译： N-in-1卡连接器
公开(公告)号：US07878858B1
公开(公告)日：2011-02-01
申请号：US12833034
申请日：2010-07-09
申请人： Chang-Hsien Tung , Tzu-Ching Tsai , Kuo-Chun Hsu
发明人： Chang-Hsien Tung , Tzu-Ching Tsai , Kuo-Chun Hsu
IPC分类号： H01R24/00
CPC分类号： H01R27/00 , G06K7/0021
摘要： An N-in-1 card connector (100), used for receiving at least two cards (a MS card A and a SD card B), includes an insulative housing (10), a number of first terminals (40) retained in the insulative housing, an ejector comprising a slider (30) moveably attached to the insulative housing, a floating member (60) floatingly received in the insulative housing and a plurality of second terminals (50) having respective parts retained with the floating member. The floating member remains at a lower position to stay clear of a first, narrower card (A) and is moveable to an upper position by a second, wider card (B). The second terminals are moveable together with the floating member at the upper position for engaging the second card.
摘要翻译：用于接收至少两张卡（MS卡A和SD卡B）的N合1卡连接器（100）包括绝缘壳体（10），多个第一终端（40）保留在绝缘壳体，包括可移动地附接到所述绝缘壳体的滑块（30）的顶出器，浮动接纳在所述绝缘壳体中的浮动构件（60）以及具有与所述浮动构件保持的各个部分的多个第二端子（50）。浮动部件保持在较低位置，以避开第一较窄的卡（A），并可通过第二较宽的卡（B）移动到上部位置。第二端子可与浮动部件一起在上部位置移动以接合第二卡。

10. 发明授权

US07500879B2 Electrical card connector 失效
标题翻译：电卡连接器
公开(公告)号：US07500879B2
公开(公告)日：2009-03-10
申请号：US11986194
申请日：2007-11-20
申请人： Chien-Jen Ting , Tzu-Ching Tsai
发明人： Chien-Jen Ting , Tzu-Ching Tsai
IPC分类号： H01R24/00
CPC分类号： H01R12/7029 , H01R13/6595
摘要： An electrical card connector includes a metal shield (2), an insulated housing (3) and a terminal module (4). The metal shield defines a receiving room, in which a memory card is insertable in a card inserting direction through an insert opening generally at a front end thereof. The insulated housing is shielded by the metal shield, and defines a receiving portion (34) extending therethrough and adjacent to a rear end thereof. The terminal module is received in the receiving portion of the insulated housing and comprises a pair of locking boards (44) assembling the terminal module on a printed circuit board (5). A plurality of terminals (31) are insert-molded in the terminal module for electrical connection to the memory card.
摘要翻译：电卡连接器包括金属屏蔽（2），绝缘外壳（3）和端子模块（4）。金属屏蔽限定了接收室，其中存储卡可以通过大致在其前端处的插入开口插入卡插入方向。绝缘壳体被金属屏蔽件屏蔽，并且限定了延伸穿过其并与其后端相邻的接收部分（34）。端子模块被容纳在绝缘壳体的接收部分中，并且包括将终端模块组装在印刷电路板（5）上的一对锁定板（44）。多个端子（31）被插入模制在端子模块中以与存储卡电连接。

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