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1. 发明申请

US20130102123A1 METHOD FOR FABRICATING SINGLE-SIDED BURIED STRAP IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于在半导体器件中制造单面凸纹的方法
公开(公告)号：US20130102123A1
公开(公告)日：2013-04-25
申请号：US13276960
申请日：2011-10-19
申请人： Tzu-Ching Tsai , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tzu-Ching Tsai , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/02
CPC分类号： H01L27/10867
摘要： A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess.
摘要翻译：一种掩埋带的制造方法包括：在半导体衬底中形成沟槽电容器结构，其中沟槽电容器结构具有掺杂多晶硅层和由掺杂多晶硅层覆盖的隔离环，以及掺杂多晶硅层的顶表面低于半导体衬底的顶表面，从而形成第一凹槽; 在半导体衬底上依次形成第一抗蚀剂层，第二抗蚀剂层和第三抗蚀剂层; 顺序地图案化第三抗蚀剂层，第二抗蚀剂层和第一抗蚀剂层，在半导体衬底上形成图案化的三层抗蚀剂层; 部分地去除由图案化的三层抗蚀剂层暴露的部分掺杂多晶硅层以形成第二凹槽; 去除图案化的三层抗蚀剂层; 以及在所述第二凹部中形成绝缘层和所述第一凹部的一部分。

2. 发明授权

US07988473B2 Electrical card connector having a shield assisting in retaining an inserted card to a slider 有权
标题翻译：具有有助于将插入的卡保持在滑块上的护罩的电子卡连接器
公开(公告)号：US07988473B2
公开(公告)日：2011-08-02
申请号：US12786461
申请日：2010-05-25
申请人： Tzu-Ching Tsai
发明人： Tzu-Ching Tsai
IPC分类号： H01R13/62
CPC分类号： H05K5/0295
摘要： An electrical card connector (100), used for receiving a card (6) having a cutout (61), includes an insulative housing (1), a plurality of contacts (2) retained in the insulative housing, a metal shield (3) covering the insulative housing to define a card receiving room (8) and a card inserting port, and an ejector (4) assembled on the insulative housing. The metal shield includes a main plate (31) and a pair of vertical walls (32) extending from the main plate. A ridge (321) is formed at one of the vertical walls. The ejector includes a slider (41), a spring member (42) and a pin member (43) for cooperatively guiding/ejecting a card. The slider has a main portion (41) extending along the card's insertion/ejection direction. The main portion forms a protruding portion (412) facing toward the card receiving room and a confronting portion (413) facing toward the one vertical wall. The protruding portion is engaged with the cutout of the card when the card is moved into a locked position in such a manner that the ridge leans against the confronting portion and presses the slider towards the card receiving room.
摘要翻译：一种用于接收具有切口（61）的卡（6）的电子卡连接器（100），包括绝缘壳体（1），保持在绝缘壳体中的多个触点（2），金属屏蔽（3）覆盖绝缘壳体以限定卡接收室（8）和卡插入口，以及组装在绝缘壳体上的喷射器（4）。金属屏蔽包括主板（31）和从主板延伸的一对垂直壁（32）。在一个垂直壁上形成脊（321）。喷射器包括用于协同地引导/弹出卡的滑块（41），弹簧构件（42）和销构件（43）。滑块具有沿卡的插入/弹出方向延伸的主要部分（41）。主要部分形成面向卡片容纳室的突出部分（412）和面向一个垂直壁的面对部分（413）。当卡以这样的方式移动到卡的位置时，突出部分与卡的切口接合，使得脊抵靠面对部分并将滑块朝向卡接收室按压。

3. 外观设计

USD638801S1 Connector 有权
公开(公告)号：USD638801S1
公开(公告)日：2011-05-31
申请号：US29361812
申请日：2010-05-14
申请人： Glenn S. Arche , Jeffrey C. Maybee , Holly K. Miyamoto , Edmond C. Choy , Tzu Ching Tsai , Min Han Lin
设计人： Glenn S. Arche , Jeffrey C. Maybee , Holly K. Miyamoto , Edmond C. Choy , Tzu Ching Tsai , Min Han Lin

4. 发明授权

US07736177B2 Electrical connector having improved contacts therein 有权
标题翻译：电连接器具有改善的接触
公开(公告)号：US07736177B2
公开(公告)日：2010-06-15
申请号：US12229643
申请日：2008-08-25
申请人： Tzu-Ching Tsai
发明人： Tzu-Ching Tsai
IPC分类号： H01R13/60
CPC分类号： H01R12/716 , H01R12/57 , H01R13/115 , H01R13/41
摘要： An electrical connector mounted on a PCB (printed circuit board) includes an insulating housing having a receiving room and a plurality of contacts retained in the insulating housing. Said insulating housing has a tongue portion and a peripheral wall surrounds said tongue portion which defines said receiving room. Each contact includes a U-shaped contacting portion received in said receiving room, a vertical holding portion retained in an inner surface of said peripheral wall and a connecting portion connecting with said contacting portion and said holding portion. Said connecting portion has a linear leading surface which is formed slanted towards said contacting portion downwardly in order to provide a smooth mating process with a mating connector.
摘要翻译：安装在PCB（印刷电路板）上的电连接器包括具有容纳室的绝缘壳体和保持在绝缘壳体中的多个触点。所述绝缘壳体具有舌部和围绕限定所述接收室的所述舌部的周壁。每个触点包括容纳在所述容纳室中的U形接触部分，保持在所述周壁的内表面中的垂直保持部分和与所述接触部分和所述保持部分连接的连接部分。所述连接部分具有向下朝向所述接触部分倾斜地形成的线性前导表面，以便与配合连接器提供平滑的配合过程。

5. 发明申请

US20090256264A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20090256264A1
公开(公告)日：2009-10-15
申请号：US12165587
申请日：2008-06-30
申请人： Yinan Chen , Hsien-Wen Liu , Tzu-Ching Tsai
发明人： Yinan Chen , Hsien-Wen Liu , Tzu-Ching Tsai
IPC分类号： H01L23/52
CPC分类号： H01L23/53295 , H01L21/76831 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided. An amorphous silicon layer that acts as a UV blocking layer replaces a conventional silicon-rich oxide (SRO) layer or the super silicon-rich oxide (SSRO) layer. By doing this, the process window is increased. In addition, silicon nitride sidewall spacer is formed inside the contact hole to prevent charge loss.
摘要翻译：提供半导体器件。作为UV阻挡层的非晶硅层代替常规富硅氧化物（SRO）层或超富硅氧化物（SSRO）层。通过这样做，过程窗口增加。此外，在接触孔内部形成氮化硅侧壁间隔物，以防止电荷损失。

6. 发明授权

US07195975B2 Method of forming bit line contact via 有权
标题翻译：形成位线接触通孔的方法
公开(公告)号：US07195975B2
公开(公告)日：2007-03-27
申请号：US10714001
申请日：2003-11-14
申请人： Tzu-Ching Tsai , Yi-Nan Chen , Hui-Min Mao
发明人： Tzu-Ching Tsai , Yi-Nan Chen , Hui-Min Mao
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L21/76897 , H01L21/76829 , H01L21/76895
摘要： A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.
摘要翻译：形成位线接触通孔的方法。该方法包括提供具有晶体管的衬底，该晶体管具有栅极，漏极区和源极区，形成覆盖漏极区的导电层，保形地形成覆盖衬底的绝缘阻挡层，覆盖在绝缘阻挡层上的绝缘层并且通过介电层和绝缘阻挡层形成通孔，暴露导电层。

7. 发明授权

US06924204B2 Split gate flash memory cell and manufacturing method thereof 有权
标题翻译：分流式闪存单元及其制造方法
公开(公告)号：US06924204B2
公开(公告)日：2005-08-02
申请号：US10605304
申请日：2003-09-22
申请人： Tzu-Ching Tsai , Yi-Nan Chen
发明人： Tzu-Ching Tsai , Yi-Nan Chen
IPC分类号： H01L21/00 , H01L21/20 , H01L21/76 , H01L21/8242
CPC分类号： H01L27/1087
摘要： A method for fabricating a buried plate of a deep trench capacitor is described. A substrate having a deep trench therein is provided. A doped layer is formed on the surface of the deep trench and a material layer is formed on the doped layer. A passivation layer is formed on the sidewall of the deep trench that is not covered by the material layer. After removing the material layer, a thermal process is conducted to drive-in the dopants in the doped layer to the substrate to form a doped region, wherein the doped region serves as a buried plate of the deep trench capacitor. The doped layer also reacts with the substrate to form an oxide layer. After removing the oxide layer, a bottle-shaped deep trench is formed.
摘要翻译：描述了制造深沟槽电容器的掩埋板的方法。提供其中具有深沟槽的衬底。在深沟槽的表面上形成掺杂层，并且在掺杂层上形成材料层。钝化层形成在深沟槽的不被材料层覆盖的侧壁上。在去除材料层之后，进行热处理以将掺杂层中的掺杂剂驱入衬底以形成掺杂区域，其中掺杂区域用作深沟槽电容器的掩埋板。掺杂层也与衬底反应以形成氧化物层。在去除氧化物层之后，形成瓶形深沟槽。

8. 发明申请

US20050037567A1 [SPLIT GATE FLASH MEMORY CELL AND MANUFACTURING METHOD THEREOF] 有权
标题翻译： [分离栅闪存存储单元及其制造方法]
公开(公告)号：US20050037567A1
公开(公告)日：2005-02-17
申请号：US10605304
申请日：2003-09-22
申请人： TZU-CHING TSAI , YI-NAN CHEN
发明人： TZU-CHING TSAI , YI-NAN CHEN
IPC分类号： H01L21/00 , H01L21/20 , H01L21/76 , H01L21/8242
CPC分类号： H01L27/1087
摘要： A method for fabricating a buried plate of a deep trench capacitor is described. A substrate having a deep trench therein is provided. A doped layer is formed on the surface of the deep trench and a material layer is formed on the doped layer. A passivation layer is formed on the sidewall of the deep trench that is not covered by the material layer. After removing the material layer, a thermal process is conducted to drive-in the dopants in the doped layer to the substrate to form a doped region, wherein the doped region serves as a buried plate of the deep trench capacitor. The doped layer also reacts with the substrate to form an oxide layer. After removing the oxide layer, a bottle-shaped deep trench is formed.
摘要翻译：描述了制造深沟槽电容器的掩埋板的方法。提供其中具有深沟槽的衬底。在深沟槽的表面上形成掺杂层，并且在掺杂层上形成材料层。钝化层形成在深沟槽的不被材料层覆盖的侧壁上。在去除材料层之后，进行热处理以将掺杂层中的掺杂剂驱入衬底以形成掺杂区域，其中掺杂区域用作深沟槽电容器的掩埋板。掺杂层也与衬底反应以形成氧化物层。在去除氧化物层之后，形成瓶形深沟槽。

9. 发明授权

US06800535B1 Method for forming bottle-shaped trenches 有权
标题翻译：形成瓶形沟槽的方法
公开(公告)号：US06800535B1
公开(公告)日：2004-10-05
申请号：US10645681
申请日：2003-08-21
申请人： Tzu-Ching Tsai , Yi-Nan Chen , Hsin-Jung Ho
发明人： Tzu-Ching Tsai , Yi-Nan Chen , Hsin-Jung Ho
IPC分类号： H01L2120
CPC分类号： H01L27/1087
摘要： A method for forming bottle-shaped trenches. First, a substrate is provided. Next, a hard mask with openings is formed on the substrate. The substrate is etched through the openings to form trenches with an upper portion and a lower portion. An isolated layer is formed conformally on the hard mask and in the trenches. A shield layer is formed in the lower portion of the trenches. A part of the insulating layer, which is not covered by the shield layer, is then removed. A protective layer is formed on the upper portion of the trenches. The shield layer and the isolated layer are removed. Finally, the substrate of the lower part of the trenches is wet etched using the protective layer as a mask so as to form bottle-shaped trenches.
摘要翻译：一种用于形成瓶形沟槽的方法。首先，提供基板。接下来，在基板上形成具有开口的硬掩模。通过开口蚀刻衬底以形成具有上部和下部的沟槽。隔离层在硬掩模和沟槽中共形地形成。在沟槽的下部形成有屏蔽层。然后除去未被屏蔽层覆盖的绝缘层的一部分。在沟槽的上部形成有保护层。去除屏蔽层和隔离层。最后，使用保护层作为掩模对沟槽下部的基底进行湿式蚀刻，以形成瓶形沟槽。

10. 发明授权

US06767800B1 Process for integrating alignment mark and trench device 有权
标题翻译：集成对准标记和沟槽器件的过程
公开(公告)号：US06767800B1
公开(公告)日：2004-07-27
申请号：US10628952
申请日：2003-07-28
申请人： Tzu-Ching Tsai , Liang-Hsin Chen
发明人： Tzu-Ching Tsai , Liang-Hsin Chen
IPC分类号： H01L2120
CPC分类号： H01L29/66181 , H01L21/308 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A process for integrating an alignment mark and a trench device. A substrate having first and second trenches is provided. The second trench is used as the alignment mark having a width larger than the first trench. The trench device is formed in each of the low portion of the first and second trenches, and then a first conductive layer is formed on the trench device in each of the first and second trenches. A second conductive layer is formed overlying the substrate and fills in the first trench and is simultaneously and conformably formed over the inner surface of the second trench. The second conductive layer and a portion of the first conductive layer in the second trench are removed and simultaneously leave a portion of the second conductive layer in the first trench by the etch back process.
摘要翻译：用于集成对准标记和沟槽装置的处理。提供具有第一和第二沟槽的衬底。第二沟槽用作具有大于第一沟槽的宽度的对准标记。沟槽器件形成在第一和第二沟槽的低部分中的每一个中，然后在沟槽器件中形成第一和第二沟槽中的每一个中的第一导电层。第二导电层形成在衬底上并且填充在第一沟槽中，同时且顺应地形成在第二沟槽的内表面上。去除第二导电层和第二沟槽中第一导电层的一部分，同时通过回蚀工艺将第二导电层的一部分留在第一沟槽中。

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