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31. 发明授权

US06759315B1 Method for selective trimming of gate structures and apparatus formed thereby 失效
标题翻译：选择性修整栅极结构的方法及由此形成的装置
公开(公告)号：US06759315B1
公开(公告)日：2004-07-06
申请号：US09224759
申请日：1999-01-04
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： H01L218238
CPC分类号： H01L21/76897 , H01L21/76888 , H01L21/76895
摘要： A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. The trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. The resulting transistor may comprise a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.
摘要翻译：在晶体管中形成修整栅极的方法包括以下步骤：在半导体衬底上形成多晶硅栅极导体，并通过从选择性表面氧化和选择性表面氮化中选择的膜生长方法来修整多晶硅部分。修整步骤可以选择性地补偿n沟道和p沟道器件。此外，修整膜可以任选地通过从各向异性和各向同性蚀刻中选择的方法去除。此外，可以通过生长膜的各向异性蚀刻形成栅极导体间隔物。所得到的晶体管可以包括栅极导体的经修剪的多晶硅部分，其中通过从选择性表面氧化和选择性表面氮化中选择的膜生长方法进行修整。

32. 发明授权

US06716647B2 Deliberate semiconductor film variation to compensate for radial processing differences, determine optimal device characteristics, or produce small productions runs 失效
标题翻译：有意识的半导体薄膜变化来补偿径向处理差异，确定最佳设备特性，或产生小的生产运行
公开(公告)号：US06716647B2
公开(公告)日：2004-04-06
申请号：US10013086
申请日：2001-12-07
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David C. Horak
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David C. Horak
IPC分类号： H01L2126
CPC分类号： H01L22/20 , C23C16/04 , C23C16/513 , C23C16/52 , H01L21/31053 , H01L21/31116 , H01L21/32137 , H01L21/76229 , H01L21/8234 , Y10S438/911
摘要： Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film. Additionally, methods and apparatuses are disclosed that can introduce deliberate semiconductor film variations to determine optimal device characteristics or produce small production runs. Introducing semiconductor film variations, such as thickness variations and/or composition variations, allow different devices to be made. A number of devices may be made having variations in semiconductor film. Because the semiconductor film has variations between the devices, device characteristics of the devices should be different. By measuring the device characteristics of devices having the variations, the device with the optimum device characteristic may be chosen, thereby indicating the appropriate semiconductor film thickness and/or composition. Moreover, small production runs of the same devices, having different characteristics, will allow the end user to select the appropriate devices for their needs.
摘要翻译：公开了可以在半导体制造期间引入有意的半导体膜变化以补偿径向处理差异，确定最佳器件特性或产生小的生产运行的方法和装置。本发明径向地改变半导体膜的厚度和/或组成，以补偿半导体膜中已知的半导体膜的径向变化，这是通过在半导体膜上进行随后的半导体处理步骤引起的。另外，公开了可以引入有意识的半导体薄膜变化以确定最佳的器件特性或产生小的生产运行。引入半导体薄膜变化，例如厚度变化和/或组成变化，允许制造不同的装置。可以制造多个器件，其具有半导体膜的变化。因为半导体薄膜在器件之间有变化，所以器件的器件特性应该是不同的。通过测量具有变化的器件的器件特性，可以选择具有最佳器件特性的器件，从而指示适当的半导体膜厚度和/或组成。此外，相同设备的小生产运行具有不同的特性，将允许最终用户根据需要选择适当的设备。

33. 发明授权

US06614074B2 Grooved planar DRAM transfer device using buried pocket 失效
标题翻译：凹槽平面DRAM传输装置采用埋式口袋
公开(公告)号：US06614074B2
公开(公告)日：2003-09-02
申请号：US09092749
申请日：1998-06-05
申请人： Gary Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , Jack A. Mandelman
发明人： Gary Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , Jack A. Mandelman
IPC分类号： H01L2976
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829
摘要： A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.
摘要翻译：一种带槽的平面DRAM传输装置，其具有形成在位于源极和漏极区域之间的衬底的沟槽中的带槽门。带槽门具有侧壁部分和限定其上的通道的底部部分。底部包括掺杂的凹穴，使得底部上的阈值电压Vt基本上小于侧壁部分上的Vt，使得侧壁部分主要控制通过该装置的电流。

34. 发明授权

US06506653B1 Method using disposable and permanent films for diffusion and implant doping 失效
标题翻译：使用一次性和永久性膜进行扩散和注入掺杂的方法
公开(公告)号：US06506653B1
公开(公告)日：2003-01-14
申请号：US09524677
申请日：2000-03-13
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L Ma , Patricia M. Marmillion , Donald W. Rakowski
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L Ma , Patricia M. Marmillion , Donald W. Rakowski
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2254 , H01L21/2255 , H01L21/823814 , H01L21/823842 , H01L29/665
摘要： Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.
摘要翻译：提供了使用一次性和永久性膜通过扩散来掺杂下层的方法。此外，提供了在植入掺杂期间使用一次性膜的方法，并且提供了用于涂覆下层材料的表面。这些一次性膜中的一些可以由传统的非一次性膜制成并制成一次性的。以这种方式，可以使用不蚀刻硅基材料的下层的溶剂。优选地，进行深度注入以形成源极/漏极区域，然后执行退火步骤以激活掺杂剂。沉积保形层并用掺杂剂注入。执行一个或多个退火步骤以在源极/漏极区域中产生非常浅的延伸。

35. 发明授权

US06387783B1 Methods of T-gate fabrication using a hybrid resist 失效
标题翻译：使用混合抗蚀剂的T型栅极制造方法
公开(公告)号：US06387783B1
公开(公告)日：2002-05-14
申请号：US09299267
申请日：1999-04-26
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： H01L2128
CPC分类号： H01L29/42316 , H01L21/28581
摘要： Methods for forming a T-gate on a substrate are provided that employ a hybrid resist. The hybrid resist specifically is employed to define a base of the T-gate on the substrate with very high resolution. To define a base of the T-gate, a hybrid resist layer is deposited on the substrate. A mask having a reticle feature with an edge is provided and is positioned above the hybrid resist layer so that the edge of the reticle feature is above a desired location for the base of the T-gate. Thereafter, the hybrid resist layer is exposed to radiation through the mask, and the exposed hybrid resist layer is developed to define an opening therein for the base of the T-gate. Preferably the loop feature formed in the hybrid resist layer by the reticle feature during exposure is trimmed. The T-gate may be completed by employing any known T-gate fabrication techniques.
摘要翻译：提供了在衬底上形成T形栅的方法，其采用混合抗蚀剂。采用混合抗蚀剂专门用于以非常高的分辨率在衬底上限定T形栅极的基极。为了限定T栅极的基极，在衬底上沉积混合抗蚀剂层。提供了具有边缘的掩模版特征的掩模，并且位于混合抗蚀剂层之上，使得掩模版特征的边缘高于用于T形栅极的基底的期望位置。此后，混合抗蚀剂层通过掩模暴露于辐射，并且暴露的混合抗蚀剂层被显影以在T形栅极的底部限定开口。优选地，在曝光期间通过掩模版特征在混合抗蚀剂层中形成的环形特征被修整。 T栅极可以通过采用任何已知的T栅极制造技术来完成。

36. 发明授权

US06333533B1 Trench storage DRAM cell with vertical three-sided transfer device 失效
标题翻译：沟槽存储DRAM单元，具有垂直三面传输设备
公开(公告)号：US06333533B1
公开(公告)日：2001-12-25
申请号：US09394964
申请日：1999-09-10
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876
摘要： A pair of dynamic random access memory cells having each end of the active area surrounded on three sides by a gate conductor. The width of each end of the active area that is surrounded by a gate conductor preferably is less than fifty percent of the width of the deep trench intersected by that end of the active area.
摘要翻译：一对动态随机存取存储器单元，其有源区域的每个端部由三个侧面由栅极导体包围。由栅极导体围绕的有源区域的每个端部的宽度优选地小于由有源区域的该端部相交的深沟槽的宽度的百分之五十。

37. 发明授权

US06333245B1 Method for introducing dopants into semiconductor devices using a germanium oxide sacrificial layer 失效
标题翻译：使用锗氧化物牺牲层将掺杂剂引入半导体器件的方法
公开(公告)号：US06333245B1
公开(公告)日：2001-12-25
申请号：US09469137
申请日：1999-12-21
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Donald W. Rakowski
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Donald W. Rakowski
IPC分类号： H01L2122
CPC分类号： H01L29/66575 , H01L21/2255 , H01L21/823814 , H01L21/823842
摘要： A method for introducing dopants into a semiconductor device using doped germanium oxide is disclosed. The method includes using rapid thermal anneal (RTA) or furnace anneal to diffuse dopants into a substrate from a doped germanium oxide sacrificial layer on the semiconductor substrate. After annealing to diffuse the dopants into the substrate, the germanium oxide sacrificial layers is removed using water thereby avoiding removal of silicon dioxide (SiO2) in the gates or in standard device isolation structures, that may lead to device failure. N+ and p+ sources and drains can be formed in appropriate wells in a semiconductor substrate, using a singular anneal and without the need to define more than one region of the first doped sacrificial layer. Alternatively, annealing before introducing a second dopant into the germanium oxide sacrificial layer give slower diffusing ions such as arsenic a head start.
摘要翻译：公开了一种使用掺杂的氧化锗将掺杂剂引入半导体器件的方法。该方法包括使用快速热退火（RTA）或炉退火来从半导体衬底上的掺杂的锗氧化物牺牲层将掺杂剂扩散到衬底中。退火之后将掺杂剂扩散到衬底中，使用水去除锗氧化物牺牲层，从而避免在栅极或标准器件隔离结构中去除二氧化硅（SiO 2），这可能导致器件故障。 N +和p +源极和漏极可以在半导体衬底中的适当的阱中使用单一退火形成，并且不需要限定第一掺杂牺牲层的不止一个区域。或者，在将第二掺杂剂引入到氧化锗牺牲层中之前的退火给出较慢的扩散离子，例如砷开始。

38. 发明授权

US06303272B1 Process for self-alignment of sub-critical contacts to wiring 失效
标题翻译：亚临界触点自动对准布线的过程
公开(公告)号：US06303272B1
公开(公告)日：2001-10-16
申请号：US09192140
申请日：1998-11-13
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： G03C500
CPC分类号： H01L21/76811 , H01L21/76813 , H01L21/76897 , H01L24/45 , H01L24/85 , H01L2224/451 , H01L2224/85 , H01L2924/00014 , H01L2924/14 , H01L2224/48 , H01L2924/00
摘要： A method for forming contacts on an integrated circuit that are self-aligned with the wiring patterns of the integrated circuit. In the method a thicker lower layer of a first material and a thinner upper layer of a second material are formed on a substrate. The features of the metal wiring is patterned first on the upper layer. The wiring pattern trenches are etched through the thinner surface layer, and partially through the second, thicker layer. After the wiring pattern is etched, the contacts for the wiring layer are printed as line/space patterns which intersect the wiring pattern. The contact pattern is etched into the lower, thicker layer with an etch process that is selective to the upper thinner layer. The contact is only formed at the intersection point of the wiring image with the contact image, therefore the contact is self-aligned to the metal.
摘要翻译：一种用于在与集成电路的布线图形自对准的集成电路上形成触点的方法。在该方法中，在衬底上形成较厚的第一材料的下层和较薄的第二材料的上层。金属布线的特征首先在上层形成。通过更薄的表面层蚀刻布线图案沟槽，并部分地穿过第二较厚的层。在布线图案被蚀刻之后，布线层的触点被印刷为与布线图案相交的线/间隔图形。通过对上部较薄层选择性的蚀刻工艺将接触图案蚀刻到下部更厚的层中。接触仅在接线图像与接触图像的交点处形成，因此触点与金属自对准。

39. 发明授权

US06258661B1 Formation of out-diffused bitline by laser anneal 失效
标题翻译：通过激光退火形成扩散位线
公开(公告)号：US06258661B1
公开(公告)日：2001-07-10
申请号：US09651614
申请日：2000-08-30
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , H01L21/2254 , H01L21/2257 , H01L21/268 , H01L21/743 , H01L27/10876
摘要： The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused bitline can also be formed utilizing an ion implantation step.
摘要翻译：本发明提供了通过利用其中沟槽区域中的掺杂剂材料扩散到半导体衬底中的激光退火步骤在半导体衬底中形成向外扩散位线的方法。外扩散位线也可以利用离子注入步骤形成。

40. 发明授权

US06207540B1 Method for manufacturing high performance MOSFET device with raised source and drain 失效
标题翻译：用于制造具有升高的源极和漏极的高性能MOSFET器件的方法
公开(公告)号：US06207540B1
公开(公告)日：2001-03-27
申请号：US09379940
申请日：1999-08-24
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Jack A. Mandelman
IPC分类号： H01L2138
CPC分类号： H01L29/66613 , H01L21/2255 , H01L29/66621 , H01L29/7834
摘要： A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion layer is connected to the edge of the device channel by extending the diffusion layer along the side wall of the trench and under a portion of the trench.
摘要翻译：一种MOSFET器件及其制造方法。该器件具有形成在硅衬底中的沟槽。设备的通道位于沟槽的底部。扩散层邻近沟槽的相对侧形成。通过沿着沟槽的侧壁和沟槽的一部分延伸扩散层，将每个扩散层连接到器件沟道的边缘。

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