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1. 发明授权

US06656807B2 Grooved planar DRAM transfer device using buried pocket 失效
公开(公告)号：US06656807B2
公开(公告)日：2003-12-02
申请号：US09772378
申请日：2001-01-30
申请人： Gary Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , Jack A. Mandelman
发明人： Gary Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , Jack A. Mandelman
IPC分类号： H01L21336
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829
摘要： A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.

2. 发明授权

US06614074B2 Grooved planar DRAM transfer device using buried pocket 失效
标题翻译：凹槽平面DRAM传输装置采用埋式口袋
公开(公告)号：US06614074B2
公开(公告)日：2003-09-02
申请号：US09092749
申请日：1998-06-05
申请人： Gary Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , Jack A. Mandelman
发明人： Gary Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , Jack A. Mandelman
IPC分类号： H01L2976
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829
摘要： A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.
摘要翻译：一种带槽的平面DRAM传输装置，其具有形成在位于源极和漏极区域之间的衬底的沟槽中的带槽门。带槽门具有侧壁部分和限定其上的通道的底部部分。底部包括掺杂的凹穴，使得底部上的阈值电压Vt基本上小于侧壁部分上的Vt，使得侧壁部分主要控制通过该装置的电流。

3. 发明授权

US06320215B1 Crystal-axis-aligned vertical side wall device 有权
标题翻译：水晶轴对齐垂直侧壁装置
公开(公告)号：US06320215B1
公开(公告)日：2001-11-20
申请号：US09359292
申请日：1999-07-22
申请人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10876
摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.
摘要翻译：一种动态随机存取存储器（DRAM）单元，其包括具有部分地设置在沟槽的侧壁上的有源晶体管器件的深沟槽存储电容器。侧壁与具有沿着单晶轴的结晶取向的第一结晶平面对准。制造这种DRAM单元的方法包括：（a）在衬底中形成深沟槽，（b）沿着具有单晶取向的沟槽侧壁形成刻面晶体区域，以及（c）形成部分设置的晶体管器件在侧壁上的刻面晶体区域上。小面晶体区域可以通过生长氧化物环形成，例如通过局部热氧化在选择的氧化条件下，以促进沿着第一晶体轴系的较高的氧化速率而不是第二晶体轴系。

4. 发明授权

US06759291B2 Self-aligned near surface strap for high density trench DRAMS 失效
标题翻译：用于高密度沟槽DRAMS的自对准近表面带
公开(公告)号：US06759291B2
公开(公告)日：2004-07-06
申请号：US10045499
申请日：2002-01-14
申请人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
发明人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
IPC分类号： H01L218234
CPC分类号： H01L27/10867
摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.
摘要翻译：一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形形结构。此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

5. 发明授权

US06426251B2 Process for manufacturing a crystal axis-aligned vertical side wall device 失效
标题翻译：用于制造晶体轴对准的垂直侧壁装置的方法
公开(公告)号：US06426251B2
公开(公告)日：2002-07-30
申请号：US09894427
申请日：2001-06-28
申请人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10876
摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.
摘要翻译：一种动态随机存取存储器（DRAM）单元，其包括具有部分地设置在沟槽的侧壁上的有源晶体管器件的深沟槽存储电容器。侧壁与具有沿着单晶轴的结晶取向的第一结晶平面对准。制造这种DRAM单元的方法包括：（a）在衬底中形成深沟槽，（b）沿着具有单晶取向的沟槽侧壁形成刻面晶体区域，以及（c）形成部分设置的晶体管器件在侧壁上的刻面晶体区域上。小面晶体区域可以通过生长氧化物环形成，例如通过局部热氧化在选择的氧化条件下，以促进沿着第一晶体轴系的较高的氧化速率而不是第二晶体轴系。

6. 发明授权

US06369419B1 Self-aligned near surface strap for high density trench DRAMS 失效
标题翻译：用于高密度沟槽DRAMS的自对准近表面带
公开(公告)号：US06369419B1
公开(公告)日：2002-04-09
申请号：US09603657
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
发明人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
IPC分类号： H01L2994
CPC分类号： H01L27/10867
摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.
摘要翻译：一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形形结构。此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

7. 发明申请

US20060128111A1 Raised sti process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain 有权
标题翻译：用于提高源/漏极的应变Si / SGOI结构的多栅极和侧壁保护的提升过程
公开(公告)号：US20060128111A1
公开(公告)日：2006-06-15
申请号：US11351801
申请日：2006-02-10
申请人： Jochen Beintner , Gary Bronner , Ramachandra Divakaruni , Byeong Kim
发明人： Jochen Beintner , Gary Bronner , Ramachandra Divakaruni , Byeong Kim
IPC分类号： H01L21/76
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

8. 发明授权

US06548357B2 Modified gate processing for optimized definition of array and logic devices on same chip 失效
标题翻译：改进的门处理，用于在同一芯片上优化阵列和逻辑器件的定义
公开(公告)号：US06548357B2
公开(公告)日：2003-04-15
申请号：US10117869
申请日：2002-04-08
申请人： Mary E. Weybright , Gary Bronner , Richard A. Conti , Ramachandra Divakaruni , Jeffrey Peter Gambino , Peter Hoh , Uwe Schroeder
发明人： Mary E. Weybright , Gary Bronner , Richard A. Conti , Ramachandra Divakaruni , Jeffrey Peter Gambino , Peter Hoh , Uwe Schroeder
IPC分类号： H01L21336
CPC分类号： H01L27/10894 , H01L21/76897 , H01L21/823456 , H01L27/1052 , H01L27/10873
摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.
摘要翻译：在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。这扩大了阵列栅极导体处理窗口。第二电介质盖层改善了支撑装置和阵列装置的线宽控制。在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

9. 发明授权

US06495876B1 DRAM strap: hydrogen annealing for improved strap resistance in high density trench DRAMS 失效
标题翻译： DRAM带：用于改善高密度沟槽DRAMS中的带状电阻的氢退火
公开(公告)号：US06495876B1
公开(公告)日：2002-12-17
申请号：US09609288
申请日：2000-06-30
申请人： Gary Bronner , Ramachandra Divakaruni , Yoichi Takegawa
发明人： Gary Bronner , Ramachandra Divakaruni , Yoichi Takegawa
IPC分类号： H01L27108
CPC分类号： H01L21/3003 , H01L27/10867
摘要： A method and structure for a DRAM device which includes a trench within an insulator, a conductor within the trench, a transistor adjacent a first side of the trench, and a shallow trench isolation region formed within a top portion of the conductor on a second side of the trench, opposite the first side, wherein the top portion of the conductor has a curved shape at an edge of the shallow trench isolation region. The curved shape comprises a conductive strap and electrically connects the conductor and the single crystal where the transistor is formed, further comprising a collar oxide surrounding the top portion of the conductor, the collar oxide controlling a shape and location of the curved shape. The curved shape is formed by hydrogen annealing, and may be convex, or concave. The DRAM further comprising a collar oxide extending into the shallow trench isolation region on the second side.
摘要翻译：一种用于DRAM器件的方法和结构，其包括绝缘体内的沟槽，沟槽内的导体，与沟槽的第一侧相邻的晶体管，以及形成在第二侧的导体的顶部内的浅沟槽隔离区所述沟槽的第一侧相对，其中所述导体的顶部在所述浅沟槽隔离区域的边缘处具有弯曲形状。弯曲形状包括导电带并且电连接导体和形成晶体管的单晶，还包括围绕导体顶部的环形氧化物，该环形氧化物控制弯曲形状的形状和位置。弯曲形状由氢退火形成，并且可以是凸形或凹形。 DRAM还包括延伸到第二侧上的浅沟槽隔离区域的环状氧化物。

10. 发明授权

US06388294B1 Integrated circuit using damascene gate structure 失效
标题翻译：集成电路采用镶嵌门结构
公开(公告)号：US06388294B1
公开(公告)日：2002-05-14
申请号：US09718571
申请日：2000-11-22
申请人： Carl Radens , Mary E. Weybright , Gary Bronner
发明人： Carl Radens , Mary E. Weybright , Gary Bronner
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/823412 , H01L21/823425 , H01L21/82345 , H01L29/665 , H01L29/66537 , H01L29/66545
摘要： An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by removing the dielectric-cap gate stack from selected regions of the semiconductor substrate and replacing the dielectric-cap gate stack with a second gate conductor which is patterned using a damascene process.
摘要翻译：提出了一种集成电路器件。本发明的集成电路器件包括半导体衬底，该半导体衬底具有使用用于自对准扩散接触（SAC）的常规绝缘栅极叠层形成的晶体管栅极的组合以及通过去除电介质帽形成的晶体管栅极结构栅堆叠从半导体衬底的选定区域，并用第二栅极导体代替介质帽栅极堆叠，第二栅极导体使用镶嵌工艺进行图案化。

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