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31. 发明申请

US20100128512A1 SEMICONDUCTOR MEMORY DEVICE HAVING CROSS-POINT STRUCTURE 审中-公开
标题翻译：具有跨点结构的半导体存储器件
公开(公告)号：US20100128512A1
公开(公告)日：2010-05-27
申请号：US12089273
申请日：2006-09-27
申请人： Tetsuya Ohnishi , Syogo Hayashi
发明人： Tetsuya Ohnishi , Syogo Hayashi
IPC分类号： G11C11/22 , G11C11/00
CPC分类号： G11C5/063 , G11C7/18 , G11C8/10 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/22 , G11C13/0023 , G11C13/003 , G11C2213/76 , G11C2213/77 , H01L27/101
摘要： A semiconductor memory device having a cross-point structure comprising a plurality of first electrode wirings extending in the same direction, a plurality of second electrode wirings intersecting with the first electrode wirings, and memory materials for storing data at the intersection points of the first and second electrode wirings has a problem that an effective voltage applied to the memory material fluctuates in a memory cell array due to the voltage drop caused by the wiring resistance of each electrode wiring. The sum of the wiring resistance of the first electrode wiring to a certain intersection point and the wiring resistance of the second electrode wiring to the certain intersection point is substantially constant at any intersection point, and the load resistors for adjusting the fluctuation of the electrode wiring resistances in a memory cell array are connected at least either one of the first and second electrode wirings.
摘要翻译：一种具有交叉点结构的半导体存储器件，包括沿相同方向延伸的多个第一电极布线，与第一电极布线相交的多个第二电极布线，以及用于在第一和第二布线的交点处存储数据的存储材料第二电极布线存在由于由每个电极布线的布线电阻引起的电压降，施加到存储器材料的有效电压在存储单元阵列中波动的问题。第一电极布线与某一交点的布线电阻和第二电极布线到某一交点的布线电阻之和在任何交点处基本恒定，并且用于调节电极布线的波动的负载电阻存储单元阵列中的电阻连接在第一和第二电极布线中的至少一个中。

32. 发明授权

US07615459B1 Manufacturing method for variable resistive element 有权
标题翻译：可变电阻元件的制造方法
公开(公告)号：US07615459B1
公开(公告)日：2009-11-10
申请号：US12190398
申请日：2008-08-12
申请人： Yushi Inoue , Tetsuya Ohnishi , Kazuya Ishihara , Takahiro Shibiuya , Yasunari Hosoi , Shinobu Yamazaki , Takashi Nakano
发明人： Yushi Inoue , Tetsuya Ohnishi , Kazuya Ishihara , Takahiro Shibiuya , Yasunari Hosoi , Shinobu Yamazaki , Takashi Nakano
IPC分类号： H01L21/20
CPC分类号： H01L45/04 , H01L45/1226 , H01L45/124 , H01L45/146 , H01L45/1633
摘要： A manufacturing method for a variable resistive element according to which a stable switching operation can be achieved with excellent reproducibility is provided. A conductive thin film is deposited on a semiconductor substrate and patterned to a predetermined form, and after that, a first interlayer insulating film is deposited. An opening is then created in a predetermined location on the first interlayer insulating film in such a manner that the upper surface of the conductive thin film is exposed and the thickness of the conductive thin film formed at the bottom of this opening is reduced through processing, and after that, an oxidation process is carried out on the periphery of the exposed conductive thin film. As a result, a variable resistor film is formed in the peripheral region of the opening, and this variable resistor film divides the conductive thin film into a first electrode and a second electrode.
摘要翻译：提供了一种可变电阻元件的制造方法，其中可以以优异的再现性实现稳定的开关操作。将导电薄膜沉积在半导体衬底上并图案化为预定形式，之后沉积第一层间绝缘膜。然后在第一层间绝缘膜上的预定位置处以导电薄膜的上表面露出并且形成在该开口底部的导电薄膜的厚度通过加工而减小的方式形成开口，之后，在露出的导电性薄膜的周围进行氧化处理。结果，在开口的周边区域中形成可变电阻膜，该可变电阻膜将导电薄膜分成第一电极和第二电极。

33. 发明授权

US07602026B2 Memory cell, semiconductor memory device, and method of manufacturing the same 有权
标题翻译：存储单元，半导体存储器件及其制造方法
公开(公告)号：US07602026B2
公开(公告)日：2009-10-13
申请号：US11474414
申请日：2006-06-26
申请人： Shinji Horii , Takashi Yokoyama , Tetsuya Ohnishi
发明人： Shinji Horii , Takashi Yokoyama , Tetsuya Ohnishi
IPC分类号： H01L23/62
CPC分类号： H01L27/101 , H01L27/2445 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1675 , H01L45/1683 , H01L2924/0002 , H01L2924/00
摘要： A memory cell in a semiconductor memory device comprises a variable resistor element configured so that a variable resistor body is sandwiched between a first electrode and a second electrode, and a transistor element capable of controlling a flow of current in the variable resistor element, wherein the transistor element and the variable resistor element are placed one over the other along a direction in which the first electrode, the variable resistor body, and the second electrode of the variable resistor element are layered, and one of the first electrode and the second electrode of the variable resistor element is connected to one electrode of the transistor element.
摘要翻译：半导体存储器件中的存储单元包括可变电阻器元件，其被配置为使得可变电阻体夹在第一电极和第二电极之间，以及晶体管元件，其能够控制可变电阻器元件中的电流流动，其中，晶体管元件和可变电阻元件沿着可变电阻器元件的第一电极，可变电阻体和第二电极层叠的方向一个放置，并且第一电极和第二电极中的一个可变电阻元件连接到晶体管元件的一个电极。

34. 发明申请

US20060154417A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20060154417A1
公开(公告)日：2006-07-13
申请号：US11330806
申请日：2006-01-11
申请人： Naoyuki Shinmura , Shigeo Ohnishi , Tetsuya Ohnishi , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri
发明人： Naoyuki Shinmura , Shigeo Ohnishi , Tetsuya Ohnishi , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri
IPC分类号： H01L21/8242
CPC分类号： H01L45/1675 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641
摘要： The present invention is directed towards a method of manufacturing a semiconductor memory device arranged of a cross point memory array having memory elements provided between upper and lower electrodes for storage of data. The present invention comprises a lower electrode lines forming step of planarizing each of the lower electrode lines and insulating layers provided on both sides of the lower electrode line so as to be substantially uniform in the height thus for patterning the lower electrode lines, a memory element layer depositing step of depositing on the lower electrode lines a memory element layer for the memory elements, and an annealing step of annealing with heat treatment either between the lower electrode lines forming step and the memory element layer depositing step or after the memory element layer depositing step so that any damages caused by the polishing of the surface of the lower electrode lines can be eliminated.
摘要翻译：本发明涉及一种制造半导体存储器件的方法，该半导体存储器件被布置成具有设置在上部和下部电极之间的存储元件的交叉点存储器阵列，用于存储数据。本发明包括下电极线，其形成步骤：将设置在下电极线两侧的每个下电极线和绝缘层平坦化，以使其高度大致均匀，从而构图下电极线;存储元件在下电极线上沉积用于存储元件的存储元件层的层沉积步骤，以及在下电极线形成步骤和存储元件层沉积步骤之间或在存储元件层沉积之后进行热处理退火的退火步骤使得可以消除由下电极线的表面的抛光引起的任何损坏。

35. 发明授权

US06750100B2 Nano-meter memory device and method of making the same 失效
标题翻译：纳米仪记忆体装置及其制作方法
公开(公告)号：US06750100B2
公开(公告)日：2004-06-15
申请号：US09940312
申请日：2001-08-27
申请人： Sheng Teng Hsu , Tomoya Baba , Tetsuya Ohnishi
发明人： Sheng Teng Hsu , Tomoya Baba , Tetsuya Ohnishi
IPC分类号： H01L218247
CPC分类号： H01L27/115 , H01L21/0337 , H01L27/11521 , Y10S438/947
摘要： A method of forming a memory device includes preparing a substrate having predefined characteristics; forming a first layer set on the substrate, including: building a first forming layer, having first form segments, on the substrate; building placeholder sidewalls on the first form segments wherein the sidewalls have a thickness of between about one nm and 100 nm; building a second forming layer, having second form segments, on the substrate between the placeholder sidewalls; removing the placeholder sidewalls forming vacated areas; and building active devices in the vacated areas.
摘要翻译：形成存储器件的方法包括制备具有预定特性的衬底; 在所述基板上形成第一层，所述第一层包括：在所述基板上构建具有第一成形段的第一形成层; 在所述第一形式段上建立占位符侧壁，其中所述侧壁具有在约1nm至100nm之间的厚度; 在占位符侧壁之间的衬底上建立具有第二形式段的第二形成层; 移除形成空置区域的占位符侧壁; 并在空置地区建设有源设备。

36. 发明授权

US5407838A Method for fabricating a semiconductor device using implantation and subsequent annealing to eliminate defects 失效
标题翻译：使用注入和随后退火制造半导体器件以消除缺陷的方法
公开(公告)号：US5407838A
公开(公告)日：1995-04-18
申请号：US196795
申请日：1994-02-15
申请人： Tetsuya Ohnishi , Kazushi Naruse
发明人： Tetsuya Ohnishi , Kazushi Naruse
IPC分类号： H01L21/265 , H01L21/331 , H01L29/73 , H01L29/732
CPC分类号： H01L21/26506 , H01L21/26513 , H01L29/66272 , Y10S148/024 , Y10S438/966 , Y10S438/98
摘要： A method for fabricating a semiconductor device including carrying out an ion implantation into a predetermined region of a single-crystal silicon substrate to form therein an amorphized ion-implanted layer according to any one of the methods: (A) implanting an ion of an atom serving as carrier into the predetermined region, followed by implanting an ion of an electrically inert atom or molecule into the region, (B) implanting an ion of an electrically inert atom or molecule in the region, followed by implanting an ion of an atom serving as carrier in the region, and (C) implanting an ion of a molecule in which an atom serving as carrier is bonded to an electrically inert atom; annealing the substrate in an inert atmosphere to crystallize the amorphized ion-implanted layer again; and further annealing the substrate in an oxidizing atmosphere to eliminate defects at the interface of the substrate and the ion implantation layer.
摘要翻译：一种用于制造半导体器件的方法，包括根据以下方法中的任一种方法将离子注入到单晶硅衬底的预定区域中以形成非晶化离子注入层：（A）注入原子离子作为载体进入预定区域，然后将电惰性原子或分子的离子注入该区域，（B）在该区域中注入电惰性原子或分子的离子，随后注入一个原子的离子作为该区域的载体，（C）将其中作为载体的原子键合的分子的离子注入到电惰性的原子上; 在惰性气氛中对衬底退火，再次使非晶化离子注入层结晶; 并且在氧化气氛中进一步退火衬底以消除衬底和离子注入层的界面处的缺陷。

37. 发明授权

US5270807A Color image processing apparatus 失效
标题翻译：彩色图像处理装置
公开(公告)号：US5270807A
公开(公告)日：1993-12-14
申请号：US842058
申请日：1992-02-26
申请人： Yoshinori Ikeda , Tetsuya Ohnishi , Masatomo Shimizu
发明人： Yoshinori Ikeda , Tetsuya Ohnishi , Masatomo Shimizu
IPC分类号： H04N1/58 , H04N1/46
CPC分类号： H04N1/58
摘要： A color image processing apparatus is disclosed wherein an edge portion of an achromatic area is detected to emphasize the edge portion and reduce the density of a chromatic area near the edge portion, and the reduced chromatic portion signal is further suppressed, such that the half tone area can be processed at high gradation and the black character and line image can be outputted in more black and with high resolution, resulting in less color bleeding.
摘要翻译：公开了一种彩色图像处理装置，其中检测到无彩色区域的边缘部分以强调边缘部分并且降低边缘部分附近的彩色区域的密度，并且还原色调部分信号被进一步抑制，使得半色调区域可以以高灰度进行处理，黑色字符和线条图像可以以更高的分辨率输出，导致较少的色彩渗色。

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