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1. 发明授权

US07511986B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07511986B2
公开(公告)日：2009-03-31
申请号：US11826613
申请日：2007-07-17
申请人： Shinji Horii , Satoru Yamagata
发明人： Shinji Horii , Satoru Yamagata
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/34 , G11C2213/79
摘要： The possibility of the loss of information stored in a memory cell which is caused by repeating the reading action on the same memory cell comprising a variable resistance element and a select transistor can significantly be reduced. A voltage applying circuit for selecting one or more of the memory cells from a memory cell array and applying voltages to the word lines, bit lines, and source lines for programming, erasing, and reading information applies a voltage between the bit line and the source line connected to the selected memory cell so that the voltage applied between the two ports of the variable resistance element in the selected memory cell during the reading action is equal in the polarity to one of the voltages applied between the two ports of the variable resistance element for the programming action and the erasing action respectively whichever is greater in the absolute value.
摘要翻译：可以显着地减少由包含可变电阻元件和选择晶体管的同一存储单元重复读取动作而导致存储在存储单元中的信息丢失的可能性。一种电压施加电路，用于从存储单元阵列中选择一个或多个存储单元，并向字线，位线和源极线施加电压用于编程，擦除和读取信息，在位线和源之间施加电压线路连接到所选择的存储器单元，使得在读取动作期间在所选择的存储单元中的可变电阻元件的两个端口之间施加的电压极性与施加在可变电阻元件的两个端口之间的电压之一相等对于编程动作和擦除动作，分别取绝对值较大者。

2. 发明授权

US07388245B2 Semiconductor device, method for manufacturing the semiconductor device and portable electronic device provided with the semiconductor device 有权
标题翻译：半导体装置，半导体装置的制造方法以及具备该半导体装置的便携式电子装置
公开(公告)号：US07388245B2
公开(公告)日：2008-06-17
申请号：US10592034
申请日：2005-03-07
申请人： Fujio Masuoka , Takashi Yokoyama , Takuji Tanigami , Shinji Horii
发明人： Fujio Masuoka , Takashi Yokoyama , Takuji Tanigami , Shinji Horii
IPC分类号： H01L29/423
CPC分类号： H01L21/28273 , H01L21/823487 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/66825 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A semiconductor device, which is characterized by that two or more island-shaped semiconductor layers including first and second island-shaped semiconductor layers are formed on the same substrate, at least the first island-shaped semiconductor layer has steps in its side wall so that sectional area of a cross section parallel to the surface of the substrate varies stepwise with respect to height in the vertical direction, the second island-shaped semiconductor layer is different from the first island-shaped semiconductor layer with respect to the presence/absence of a step in the side wall or the number of steps, and each of the first and second island-shaped semiconductor layers provides an element on a stair part of the side wall divided by the steps or on the side wall having no steps.
摘要翻译：一种半导体器件，其特征在于，在同一衬底上形成包括第一和第二岛状半导体层的两个或多个岛状半导体层，至少第一岛状半导体层在其侧壁上具有台阶，使得与基板的表面平行的截面的截面积相对于垂直方向的高度逐步变化，第二岛状半导体层相对于第一岛状半导体层的存在/不存在而不同第一和第二岛状半导体层中的每一个在侧壁分隔的侧壁的台阶部分或不具有台阶的侧壁上提供元件。

3. 发明授权

US07088617B2 Nonvolatile semiconductor storage device, and liquid crystal display device including the same 有权
标题翻译：非易失性半导体存储装置以及包含该非易失性半导体存储装置的液晶显示装置
公开(公告)号：US07088617B2
公开(公告)日：2006-08-08
申请号：US10919777
申请日：2004-08-16
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
IPC分类号： G11C16/04
CPC分类号： G11C16/0483
摘要： A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in the respective memory cell unit groups are each uniquely selected on the basis of a combination of the common control gate line and the first and second common selection gate lines.
摘要翻译：一种非易失性半导体存储装置，包括：多个存储单元单元组，每个存储单元单元组包括一个或多个NAND非易失性存储单元单元，每个非易失性存储单元单元包括至少一个具有控制栅极的存储单元，晶体管具有第二选择栅极，所述存储单元单元组还包括连接到所述控制栅极的控制栅极线，连接到所述第一选择栅极的第一选择栅极线和连接到所述第二选择栅极的第二选择栅极线; 公共控制栅极线，共同地连接到不同的存储单元单元组的控制栅极线; 第一公共选择栅极线，共同连接到不同的存储单元单元组的第一选择栅极线; 以及第二公共选择栅极线，共同连接到不同的存储单元单元组的第二选择栅极线; 其中各个存储单元单元组中的存储单元是基于公共控制栅极线和第一和第二公共选择栅极线的组合而被唯一地选择的。

4. 发明授权

US07061038B2 Semiconductor memory device and its production process 有权
标题翻译：半导体存储器件及其生产工艺
公开(公告)号：US07061038B2
公开(公告)日：2006-06-13
申请号：US10727266
申请日：2003-12-04
申请人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Shinji Horii
发明人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Shinji Horii
IPC分类号： H01L29/76
CPC分类号： H01L27/0207 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11519 , H01L27/11553 , H01L27/11556 , H01L27/11568 , H01L27/1203 , H01L29/0692 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： The present invention provides a semiconductor memory device comprising: a first conductivity type semiconductor substrate; and a plurality of memory cells constituted of an island-like semiconductor layer which is formed on the semiconductor substrate, and a charge storage layer and a control gate which are formed entirely or partially around a sidewall of the island-like semiconductor layer, wherein the plurality of memory cells are disposed in series, the island-like semiconductor layer which constitutes the memory cells has cross-sectional areas varying in stages in a horizontal direction of the semiconductor substrate, and an insulating film capable of passing charges is provided at least in a part of a plane of the island-like semiconductor layer horizontal to the semiconductor substrate.
摘要翻译：本发明提供一种半导体存储器件，包括：第一导电型半导体衬底; 以及由在半导体衬底上形成的岛状半导体层和电荷存储层和控制栅极构成的多个存储单元，其形成在岛状半导体层的侧壁的整个或部分周围，其中，多个存储单元被串联设置，构成存储单元的岛状半导体层具有在半导体衬底的水平方向上分级变化的横截面区域，并且能够至少在岛状半导体层的与半导体衬底水平的平面的一部分。

5. 发明授权

US07060598B2 Method for implanting ions into semiconductor substrate 有权
标题翻译：将离子注入半导体衬底的方法
公开(公告)号：US07060598B2
公开(公告)日：2006-06-13
申请号：US10918515
申请日：2004-08-12
申请人： Fujio Masuoka , Shinji Horii , Takuji Tanigami , Takashi Yokoyama
发明人： Fujio Masuoka , Shinji Horii , Takuji Tanigami , Takashi Yokoyama
IPC分类号： H01L21/425
CPC分类号： H01L21/26586
摘要： An ion implantation method for implanting ions into a side wall of a protruded semiconductor layer from a semiconductor substrate, the method includes applying an electric field to accelerate the ions in one direction and applying a magnetic field parallel to a plane extending at a predetermined angle with respect to the one direction, thereby controlling a direction of the ion implantation to the side wall.
摘要翻译：一种用于从半导体衬底将离子注入到突出的半导体层的侧壁中的离子注入方法，所述方法包括：施加电场以加速沿一个方向的离子，并施加平行于以预定角度延伸的平面的磁场与相对于该一个方向，从而控制离子注入到侧壁的方向。

6. 发明申请

US20050224847A1 Semiconductor memory device and manufacturing method for the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20050224847A1
公开(公告)日：2005-10-13
申请号：US11084648
申请日：2005-03-16
申请人： Fujio Masuoka , Shinji Horii , Takuji Tanigami , Takashi Yokoyama
发明人： Fujio Masuoka , Shinji Horii , Takuji Tanigami , Takashi Yokoyama
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/76 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66825 , H01L27/115 , H01L27/11556 , H01L29/7887 , H01L29/7923
摘要： The present invention provides a semiconductor memory device including: a semiconductor substrate of a first conductivity type; and a memory cell including: (i) a columnar semiconductor portion formed on the substrate, (ii) at least two charge-storage layers formed around a periphery of the columnar semiconductor portion and divided in a direction vertical to the semiconductor substrate, and (iii) a control gate that covers at least a portion of charge-storage layers, wherein the memory cell is capable of holding two-bit or more data.
摘要翻译：本发明提供一种半导体存储器件，包括：第一导电类型的半导体衬底; 以及存储单元，包括：（i）形成在所述基板上的柱状半导体部，（ii）形成在所述柱状半导体部的周围的并且沿与所述半导体基板垂直的方向分割的至少两个电荷存储层，和 iii）覆盖电荷存储层的至少一部分的控制栅极，其中所述存储器单元能够保持两位或更多数据。

7. 发明申请

US20050101087A1 Semiconductor memory device and its production process 有权
标题翻译：半导体存储器件及其生产工艺
公开(公告)号：US20050101087A1
公开(公告)日：2005-05-12
申请号：US10727266
申请日：2003-12-04
申请人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Shinji Horii
发明人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Shinji Horii
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/84 , H01L27/02 , H01L27/115 , H01L27/12 , H01L29/06 , H01L29/788 , H01L29/792
CPC分类号： H01L27/0207 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11519 , H01L27/11553 , H01L27/11556 , H01L27/11568 , H01L27/1203 , H01L29/0692 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： The present invention provides a semiconductor memory device comprising: a first conductivity type semiconductor substrate; and a plurality of memory cells constituted of an island-like semiconductor layer which is formed on the semiconductor substrate, and a charge storage layer and a control gate which are formed entirely or partially around a sidewall of the island-like semiconductor layer, wherein the plurality of memory cells are disposed in series, the island-like semiconductor layer which constitutes the memory cells has cross-sectional areas varying in stages in a horizontal direction of the semiconductor substrate, and an insulating film capable of passing charges is provided at least in a part of a plane of the island-like semiconductor layer horizontal to the semiconductor substrate.
摘要翻译：本发明提供一种半导体存储器件，包括：第一导电型半导体衬底; 以及由在半导体衬底上形成的岛状半导体层和电荷存储层和控制栅极构成的多个存储单元，其形成在岛状半导体层的侧壁的整个或部分周围，其中，多个存储单元被串联设置，构成存储单元的岛状半导体层具有在半导体衬底的水平方向上分级变化的横截面区域，并且能够至少在岛状半导体层的与半导体衬底水平的平面的一部分。

8. 发明授权

US07619675B2 Solid-state image taking apparatus with photoelectric converting and vertical charge transferring sections and method for fabricating the same 失效
标题翻译：具有光电转换和垂直电荷转移部分的固态摄像装置及其制造方法
公开(公告)号：US07619675B2
公开(公告)日：2009-11-17
申请号：US11175042
申请日：2005-07-06
申请人： Shinji Horii
发明人： Shinji Horii
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H01L27/14687 , H01L27/14623 , H01L27/14656 , H01L27/14806 , H01L27/14812 , H04N5/335
摘要： A solid-state image pickup apparatus includes one or a plurality of photoelectric converting sections for photoelectric converting incident light into a signal charge on a semiconductor substrate, and a vertical charge-transferring section for charge-transferring the signal charge photoelectric converted at the photoelectric converting section, in which the vertical charge-transferring section is located under the photoelectric converting section on the side of the semiconductor substrate.
摘要翻译：固体摄像装置包括一个或多个光电转换部分，用于将入射光光电转换成半导体衬底上的信号电荷;以及垂直电荷转移部分，用于对在光电转换处转换的信号电荷进行电荷转移其中垂直电荷转移部分位于半导体衬底侧的光电转换部分的下方。

9. 发明申请

US20080025070A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20080025070A1
公开(公告)日：2008-01-31
申请号：US11826613
申请日：2007-07-17
申请人： Shinji Horii , Satoru Yamagata
发明人： Shinji Horii , Satoru Yamagata
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/34 , G11C2213/79
摘要： The possibility of the loss of information stored in a memory cell which is caused by repeating the reading action on the same memory cell comprising a variable resistance element and a select transistor can significantly be reduced. A voltage applying circuit for selecting one or more of the memory cells from a memory cell array and applying voltages to the word lines, bit lines, and source lines for programming, erasing, and reading information applies a voltage between the bit line and the source line connected to the selected memory cell so that the voltage applied between the two ports of the variable resistance element in the selected memory cell during the reading action is equal in the polarity to one of the voltages applied between the two ports of the variable resistance element for the programming action and the erasing action respectively whichever is greater in the absolute value.
摘要翻译：可以显着地减少由包含可变电阻元件和选择晶体管的同一存储单元重复读取动作而导致存储在存储单元中的信息丢失的可能性。一种电压施加电路，用于从存储单元阵列中选择一个或多个存储单元，并向字线，位线和源极线施加电压用于编程，擦除和读取信息，在位线和源之间施加电压线路连接到所选择的存储器单元，使得在读取动作期间在所选择的存储单元中的可变电阻元件的两个端口之间施加的电压极性与施加在可变电阻元件的两个端口之间的电压之一相等对于编程动作和擦除动作，分别取绝对值较大者。

10. 发明申请

US20070278625A1 Semiconductor Device, Method For Manufacturing The Semiconductor Device And Portable Electronic Device Provided With The Semiconductor Device 有权
标题翻译：半导体装置，半导体装置的半导体装置及便携式电子装置的制造方法
公开(公告)号：US20070278625A1
公开(公告)日：2007-12-06
申请号：US10592034
申请日：2005-03-07
申请人： Fujio Masuoka , Takashi Yokoyama , Takuji Tanigami , Shinji Horii
发明人： Fujio Masuoka , Takashi Yokoyama , Takuji Tanigami , Shinji Horii
IPC分类号： H01L23/48 , H01L21/20
CPC分类号： H01L21/28273 , H01L21/823487 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/66825 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A semiconductor device, which is characterized by that two or more island-shaped semiconductor layers including first and second island-shaped semiconductor layers are formed on the same substrate, at least the first island-shaped semiconductor layer has steps in its side wall so that sectional area of a cross section parallel to the surface of the substrate varies stepwise with respect to height in the vertical direction, the second island-shaped semiconductor layer is different from the first island-shaped semiconductor layer with respect to the presence/absence of a step in the side wall or the number of steps, and each of the first and second island-shaped semiconductor layers provides an element on a stair part of the side wall divided by the steps or on the side wall having no steps.
摘要翻译：一种半导体器件，其特征在于，在同一衬底上形成包括第一和第二岛状半导体层的两个或多个岛状半导体层，至少第一岛状半导体层在其侧壁上具有台阶，使得与基板的表面平行的截面的截面积相对于垂直方向的高度逐步变化，第二岛状半导体层相对于第一岛状半导体层的存在/不存在而不同第一和第二岛状半导体层中的每一个在侧壁分隔的侧壁的台阶部分或不具有台阶的侧壁上提供元件。

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