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1. 发明授权

US06750100B2 Nano-meter memory device and method of making the same 失效
标题翻译：纳米仪记忆体装置及其制作方法
公开(公告)号：US06750100B2
公开(公告)日：2004-06-15
申请号：US09940312
申请日：2001-08-27
申请人： Sheng Teng Hsu , Tomoya Baba , Tetsuya Ohnishi
发明人： Sheng Teng Hsu , Tomoya Baba , Tetsuya Ohnishi
IPC分类号： H01L218247
CPC分类号： H01L27/115 , H01L21/0337 , H01L27/11521 , Y10S438/947
摘要： A method of forming a memory device includes preparing a substrate having predefined characteristics; forming a first layer set on the substrate, including: building a first forming layer, having first form segments, on the substrate; building placeholder sidewalls on the first form segments wherein the sidewalls have a thickness of between about one nm and 100 nm; building a second forming layer, having second form segments, on the substrate between the placeholder sidewalls; removing the placeholder sidewalls forming vacated areas; and building active devices in the vacated areas.
摘要翻译：形成存储器件的方法包括制备具有预定特性的衬底; 在所述基板上形成第一层，所述第一层包括：在所述基板上构建具有第一成形段的第一形成层; 在所述第一形式段上建立占位符侧壁，其中所述侧壁具有在约1nm至100nm之间的厚度; 在占位符侧壁之间的衬底上建立具有第二形式段的第二形成层; 移除形成空置区域的占位符侧壁; 并在空置地区建设有源设备。

2. 发明授权

US07905013B2 Method for forming an iridium oxide (IrOx) nanowire neural sensor array 有权
标题翻译：形成氧化铱（IrOx）纳米线神经传感器阵列的方法
公开(公告)号：US07905013B2
公开(公告)日：2011-03-15
申请号：US11809959
申请日：2007-06-04
申请人： Fengyan Zhang , Bruce D. Ulrich , Wei Gao , Sheng Teng Hsu
发明人： Fengyan Zhang , Bruce D. Ulrich , Wei Gao , Sheng Teng Hsu
IPC分类号： H01K3/10
CPC分类号： A61N1/0543 , B82Y15/00 , B82Y30/00 , Y10T29/49128 , Y10T29/4913 , Y10T29/49165 , Y10T29/49167 , Y10T29/49169 , Y10T428/24998
摘要： An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.
摘要翻译：提供氧化铱（IrOx）纳米线神经传感器阵列及相关制造方法。该方法提供了具有覆盖在衬底上的导电层的衬底和覆盖导电层的电介质层。基板可以是诸如Si，SiO 2，石英，玻璃或聚酰亚胺的材料，并且导电层是诸如ITO，SnO 2，ZnO，TiO 2，掺杂的ITO，掺杂的SnO 2，掺杂的ZnO，掺杂的TiO 2，TiN， TaN，Au，Pt或Ir。电介质层被选择性地湿蚀刻，与电介质层中的倾斜壁形成接触孔并且暴露导电层的区域。 IrOx纳米线神经接口从导电层的暴露区域生长。 IrOx纳米线神经接口各自具有在0.5至10微米的范围内的横截面，并且可以被成形为圆形，矩形或椭圆形。

3. 发明授权

US07811913B2 Method of fabricating a low, dark-current germanium-on-silicon pin photo detector 有权
标题翻译：制造低，暗电流硅 - 硅引脚光电探测器的方法
公开(公告)号：US07811913B2
公开(公告)日：2010-10-12
申请号：US11312967
申请日：2005-12-19
申请人： Jong-Jan Lee , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/265
CPC分类号： H01L31/105 , H01L31/1808 , H01L31/1864 , Y02E10/50 , Y02P70/521 , Y10S438/933
摘要： A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the boron-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.
摘要翻译：制造低，暗电流锗硅PIN光检测器的方法包括制备P型硅晶片; 用硼离子注入P型硅晶片; 激活硼离子以在硅晶片上形成P +区; 在P +硅表面上形成硼掺杂锗层; 在硼掺杂的锗层上沉积本征锗层; 循环退火，包括相对高温的第一退火步骤和相对低温的第二退火步骤; 重复第一和第二退火步骤约20个循环，由此迫使晶体缺陷到P +锗层; 在锗层表面注入离子以形成N +锗表面层和PIN二极管; 通过热退火来活化N +锗表面层; 并根据已知技术完成器件以形成低暗电流锗硅PIN光电探测器。

4. 发明授权

US07759756B2 Dual-pixel full color CMOS imager 有权
标题翻译：双像素全彩CMOS成像仪
公开(公告)号：US07759756B2
公开(公告)日：2010-07-20
申请号：US12025618
申请日：2008-02-04
申请人： Jong-Jan Lee , Sakae Wada , Sheng Teng Hsu
发明人： Jong-Jan Lee , Sakae Wada , Sheng Teng Hsu
IPC分类号： H01L31/00 , H01L31/062 , H01L31/113
CPC分类号： H01L27/14647 , H01L27/14689
摘要： A dual-pixel full color complementary metal oxide semiconductor (CMOS) imager is provided, along with an associated fabrication process. Two stand-alone pixels are used for three-color detection. The first pixel is a single photodiode, and the second pixel has two photodiodes built in a stacked structure. The two photodiode stack includes an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. The single photodiode includes the n doped substrate, a p doped layer overlying the substrate, and an n doped layer cathode overlying the p doped layer.
摘要翻译：提供了双像素全色互补金属氧化物半导体（CMOS）成像器，以及相关的制造工艺。两个独立像素用于三色检测。第一像素是单个光电二极管，第二像素具有以堆叠结构内置的两个光电二极管。两个光电二极管堆叠包括n掺杂衬底，底部光电二极管和顶部光电二极管。底部光电二极管具有覆盖衬底的底部p掺杂层和覆盖底部p掺杂层的底部n掺杂层阴极。顶部光电二极管具有覆盖底部n掺杂层的顶部p掺杂层和覆盖顶部p掺杂层的顶部n掺杂层阴极。单个光电二极管包括n掺杂衬底，覆盖衬底的p掺杂层和覆盖p掺杂层的n掺杂层阴极。

5. 发明授权

US07723729B2 Compound semiconductor-on-silicon wafer with a silicon nanowire buffer layer 有权
标题翻译：具有硅纳米线缓冲层的复合半导体硅片
公开(公告)号：US07723729B2
公开(公告)日：2010-05-25
申请号：US12036396
申请日：2008-02-25
申请人： Tingkai Li , Sheng Teng Hsu
发明人： Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L31/0312 , H01L29/20 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/02381 , H01L21/02433 , H01L21/02447 , H01L21/0245 , H01L21/02502 , H01L21/0254 , H01L21/02546 , H01L21/02639 , H01L21/0265 , H01L29/045 , H01L29/0673
摘要： A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips. A lateral epitaxial overgrowth (LEO) process grows compound semiconductor from the compound semiconductor-coated Si nanowire tips, to form a compound semiconductor layer overlying the insulator. Typically, the insulator layer overlying the Si substrate is a thermally soft insulator (TSI), silicon dioxide, or SiXNY, where x≦3 and Y≦4. The compound semiconductor can be GaN, GaAs, GaAlN, or SiC. In one aspect, the Si nanowire tips are carbonized, and SiC is selectively deposited overlying the carbonized Si nanowire tips, prior to the selective deposition of compound semiconductor on the Si nanowire tips.
摘要翻译：提供了具有Si纳米线缓冲层的化合物半导体硅（Si）晶片以及相应的制造方法。该方法形成Si衬底。在Si衬底上形成绝缘体层，Si纳米线具有暴露的尖端。化合物半导体选择性沉积在Si纳米线尖端上。横向外延生长（LEO）工艺从化合物半导体涂覆的Si纳米线尖端生长化合物半导体，以形成覆盖绝缘体的化合物半导体层。通常，覆盖Si衬底的绝缘体层是热软绝缘体（TSI），二氧化硅或SiXNY，其中x和nlE; 3和Y和nlE; 4。化合物半导体可以是GaN，GaAs，GaAlN或SiC。在一个方面，将Si纳米线尖端碳化，并且在Si纳米线尖端上选择性沉积化合物半导体之前，选择性地将SiC沉积在碳化Si纳米线尖端上。

6. 发明授权

US07651883B2 High energy implant photodiode stack 失效
标题翻译：高能注入光电二极管叠层
公开(公告)号：US07651883B2
公开(公告)日：2010-01-26
申请号：US11801320
申请日：2007-05-09
申请人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L27/14647 , H01L27/1463 , H01L27/14689
摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, with a corresponding fabrication process. The color imager cell array is formed from a bulk silicon (Si) substrate without an overlying epitaxial Si layer. A plurality of color imager cells are formed in the bulk Si substrate, where each color imager cell includes a photodiode set and a U-shaped well liner. The photodiode set includes first, second, and third photodiode formed as a stacked multi-junction structure, while the U-shaped well liner fully isolates the photodiode set from adjacent photodiode sets in the array. The U-shaped well liner includes a physically interfacing doped well liner bottom and first wall. The well liner bottom is interposed between the substrate and the photodiode set, and the first wall physically interfaces each doped layer of each photodiode in the photodiode set.
摘要翻译：提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，具有相应的制造工艺。彩色成像器单元阵列由体硅（Si）衬底形成，而不具有上覆的外延Si层。在本体Si衬底中形成多个彩色成像器单元，其中每个彩色成像器单元包括光电二极管组和U形衬管。光电二极管组包括形成为堆叠多结结构的第一，第二和第三光电二极管，而U形阱衬套将光电二极管组与阵列中的相邻光电二极管组完全隔离。 U形井衬管包括物理接口掺杂的井筒底部和第一壁。阱衬底位于衬底和光电二极管组之间，并且第一壁物理地连接光电二极管组中每个光电二极管的每个掺杂层。

7. 发明授权

US07651880B2 Ge short wavelength infrared imager 有权
标题翻译： Ge短波长红外成像仪
公开(公告)号：US07651880B2
公开(公告)日：2010-01-26
申请号：US11592465
申请日：2006-11-04
申请人： Douglas J. Tweet , Jer-Shen Maa , Jong-Jan Lee , Sheng Teng Hsu
发明人： Douglas J. Tweet , Jer-Shen Maa , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L25/00
CPC分类号： H01L31/1055 , H01L27/14643 , H01L27/14689
摘要： A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.
摘要翻译：提供锗（Ge）短波长红外（SWIR）成像器和相关制造工艺。该成像器包括具有掺杂阱的硅（Si）衬底。在位于Si衬底上的松弛的含Ge膜中形成一个pin二极管阵列，每个pin二极管具有倒装芯片接口。存在Ge / Si界面和插入含Ge膜和Ge / Si界面之间的含掺杂Ge的缓冲层。 Si CMOS读出电路阵列结合到倒装芯片接口。每个读出电路都具有零伏二极管偏置接口。

8. 发明授权

US07633108B2 Metal/semiconductor/metal current limiter 有权
标题翻译：金属/半导体/金属限流器
公开(公告)号：US07633108B2
公开(公告)日：2009-12-15
申请号：US11893402
申请日：2007-08-15
申请人： Tingkai Li , Sheng Teng Hsu , Wei-Wei Zhuang , David R. Evans
发明人： Tingkai Li , Sheng Teng Hsu , Wei-Wei Zhuang , David R. Evans
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method provides a substrate; forms an MSM bottom electrode overlying the substrate; forms a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forms an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).
摘要翻译：提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。该方法提供基底; 形成覆盖衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnOx半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

9. 发明授权

US07625595B2 Method of monitoring PCMO precursor synthesis 有权
标题翻译：监测PCMO前体合成的方法
公开(公告)号：US07625595B2
公开(公告)日：2009-12-01
申请号：US11403022
申请日：2006-04-11
申请人： Wei-Wei Zhuang , David R. Evans , Tingkai Li , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , David R. Evans , Tingkai Li , Sheng Teng Hsu
IPC分类号： B05D5/12
CPC分类号： H01L22/20 , H01L21/31691 , H01L22/14
摘要： A method of monitoring synthesis of PCMO precursor solutions includes preparing a PCMO precursor solution and withdrawing samples of the precursor solution at intervals during a reaction phase of the PCMO precursor solution synthesis. The samples of the PCMO precursor solution are analyzed by UV spectroscopy to determine UV transmissivity of the samples of the PCMO precursor solution and the samples used to form PCMO thin films. Electrical characteristics of the PCMO thin films formed from the samples are determined to identify PCMO thin films having optimal electrical characteristics. The UV spectral characteristics of the PCMO precursor solutions are correlated with the PCMO thin films having optimal electrical characteristics. The UV spectral characteristics are used to monitor synthesis of future batches of the PCMO precursor solutions, which will result in PCMO thin films having optimal electrical characteristics.
摘要翻译：监测PCMO前体溶液合成的方法包括制备PCMO前体溶液，并在PCMO前体溶液合成反应期间间隔取出前体溶液样品。通过紫外光谱分析PCMO前体溶液的样品，以确定PCMO前体溶液和用于形成PCMO薄膜的样品的UV透射率。确定由样品形成的PCMO薄膜的电特性以鉴定具有最佳电特性的PCMO薄膜。 PCMO前体溶液的UV光谱特性与具有最佳电学特性的PCMO薄膜相关。 UV光谱特性用于监测未来批次的PCMO前体溶液的合成，这将导致具有最佳电特性的PCMO薄膜。

10. 发明申请

US20090173933A1 Thermal Sensor with a Silicon/Germanium Superlattice Structure 有权
标题翻译：具有硅/锗超晶格结构的热传感器
公开(公告)号：US20090173933A1
公开(公告)日：2009-07-09
申请号：US12236480
申请日：2008-09-23
申请人： Jer-Shen Maa , Jinke Tang , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jer-Shen Maa , Jinke Tang , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L29/15
CPC分类号： H01L31/035254 , B82Y20/00 , H01L27/14649 , H01L31/028 , H01L31/101 , H01L31/1804 , Y02P70/521
摘要： A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.
摘要翻译：硅/锗（SiGe）超晶格热传感器具有相应的制造方法。该方法在第一Si衬底中形成有源CMOS器件，并在第二绝缘体上（SOI）衬底上形成SiGe超晶格结构。第一基板与第二基板接合，形成接合基板。在SiGe超晶格结构和CMOS器件之间形成电连接，并且在SiGe超晶格结构和键合衬底之间形成空穴。

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