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31. 发明授权

US4367520A Method and apparatus for controlling pulse width modulation inverter circuit 失效
标题翻译：控制脉宽调制逆变电路的方法和装置
公开(公告)号：US4367520A
公开(公告)日：1983-01-04
申请号：US221320
申请日：1980-12-29
申请人： Nobuyoshi Muto , Yasuo Matsuda , Shigeki Morinaga , Yasuyuki Sugiura
发明人： Nobuyoshi Muto , Yasuo Matsuda , Shigeki Morinaga , Yasuyuki Sugiura
IPC分类号： H02P27/08 , H02M7/48 , H02M7/527 , H02M1/12
CPC分类号： H02M7/527
摘要： A pulse width modulation inverter in which a staircase wave signal is used as the modulating wave. The number M of the stair steps of the staircase wave signal is set at a given integer in a range defined by 2.ltoreq.M.ltoreq.(N-3)/2 where N represents the number of the carrier waves appearing during a half period of the staircase wave and an odd integer not smaller than 7.
摘要翻译：使用阶梯波信号作为调制波的脉宽调制反相器。梯形波信号的台阶数M设定在由2

32. 发明申请

US20110181222A1 MOTOR CONTROL SYSTEM AND METHOD 审中-公开
标题翻译：电机控制系统及方法
公开(公告)号：US20110181222A1
公开(公告)日：2011-07-28
申请号：US13015035
申请日：2011-01-27
申请人： Hiroshi NAGASE , Shigeki Morinaga , Yasuhiko Tanaka , Masataka Yahara , Tetsuro Kobayashi
发明人： Hiroshi NAGASE , Shigeki Morinaga , Yasuhiko Tanaka , Masataka Yahara , Tetsuro Kobayashi
IPC分类号： H02P6/08
CPC分类号： H02P5/68 , H02P21/00 , H02P2207/05
摘要： A highly efficient and reliable motor control system and motor control method are provided. The motor control system includes a motor having a plurality of sets of armature windings, a plurality of inverters which drive the plurality of sets of armature windings, and a plurality of control devices which control the inverters individually. In the motor control system: while a motor torque command is in a smallest-magnitude range, a first inverter is operated to energize a first set of armature windings; when the motor torque command increases into a next larger-magnitude range, the first and a second inverter are operated to energize the first and a second set of armature windings; when the motor torque command increases into a still next larger-magnitude range, the first, the second, and a third inverter are operated to energize the first, the second, and a third set of armature windings; and when the motor torque command increases into a largest-magnitude range, all inverters are operated to energize all sets of armature windings. Thus, the number of inverters driven and/or the number of sets of armature windings energized are sequentially changed according to the torque command.
摘要翻译：提供高效可靠的电机控制系统和电机控制方法。电动机控制系统包括具有多组电枢绕组的电动机，驱动多组电枢绕组的多个逆变器和分别控制逆变器的多个控制装置。在电动机控制系统中：当电动机转矩指令处于最小幅度范围时，第一逆变器被操作以激励第一组电枢绕组; 当电动机转矩指令增加到下一较大幅度范围时，第一和第二逆变器被操作以激励第一和第二组电枢绕组; 当电动机转矩指令增加到下一个更大幅度的范围时，第一，第二和第三逆变器被操作以激励第一组，第二组和第三组电枢绕组; 并且当电动机转矩指令增加到最大幅度范围时，所有逆变器都被操作以对所有的电枢绕组组通电。因此，驱动的逆变器的数量和/或通电的电枢绕组的数量的数量根据转矩指令而顺序地改变。

33. 发明授权

US5642499A Method and apparatus for controlling timing of execution of saving and restoring operations in a processor system 失效
标题翻译：用于控制处理器系统中的保存和恢复操作的执行时序的方法和装置
公开(公告)号：US5642499A
公开(公告)日：1997-06-24
申请号：US223834
申请日：1994-04-06
申请人： Mamoru Ohba , Shigeki Morinaga , Mitsuru Watabe , Hiroyuki Kida
发明人： Mamoru Ohba , Shigeki Morinaga , Mitsuru Watabe , Hiroyuki Kida
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F11/28 , G06F15/16 , G06F15/177
CPC分类号： G06F9/461 , G06F9/30025 , G06F9/3861 , G06F9/3885
摘要： In a coprocessor system having a central processing unit (CPU), a floating-point processing unit (FPU) and a memory (RAM), coupled with each other through buses, when the CPU issues a save command to the FPU, the FPU discriminates the attribute, i.e., a long command or a short command, of a current command executed by the FPU upon receipt of the save command and the internal status thereof. In response to the discrimination result, the FPU interrupts the execution of the current command at once to start the execution of the received save command, when the current command is a long command, and the FPU executes the received save command after the completion of execution of the current command, if the current command is a short command. The attribute of a command is determined in advance on the basis of a time necessary for executing the command and a predetermined criterion provided therefor.
摘要翻译：在具有中央处理单元（CPU）的协处理器系统中，当CPU向FPU发出保存命令时，通过总线彼此耦合的浮点处理单元（FPU）和存储器（RAM），FPU鉴别 FPU在接收到保存命令及其内部状态时执行的当前命令的属性，即长命令或短命令。响应于鉴别结果，FPU一旦中断当前命令的执行，开始执行接收到的保存命令，当前命令为长命令，并且FPU在执行完成后执行接收到的保存命令的当前命令，如果当前命令是一个短命令。基于执行命令所需的时间和为此提供的预定标准，预先确定命令的属性。

34. 发明授权

US5490064A Control unit for vehicle and total control system therefor 失效
标题翻译：车辆控制单元及总控制系统
公开(公告)号：US5490064A
公开(公告)日：1996-02-06
申请号：US280930
申请日：1994-07-26
申请人： Toshimichi Minowa , Yoshiyuki Yoshida , Junichi Ishii , Shigeki Morinaga , Hiroshi Katayama , Mitsuo Kayano , Kenichiro Kurata
发明人： Toshimichi Minowa , Yoshiyuki Yoshida , Junichi Ishii , Shigeki Morinaga , Hiroshi Katayama , Mitsuo Kayano , Kenichiro Kurata
IPC分类号： B60W50/00 , F01N11/00 , F02D37/02 , F02D41/26 , G01R31/28 , G05B19/00 , G05B19/042 , G05D1/00 , G06F7/70 , G06F12/08 , G06F19/00 , G06F9/06
CPC分类号： F02D41/26 , F01N11/007 , F02D37/02 , F02D41/263 , F02D41/266 , G05B19/00 , G05B19/0423 , G06F8/65 , B60W2050/0005 , F01N2550/02 , F01N2900/0422 , F02D2041/285 , F02D2200/0404 , F02D2200/0406 , F02D2200/501 , F02D41/1454 , F02D41/187 , G05B2219/21015 , G05B2219/21021 , G05B2219/21127 , G05B2219/21137 , G05B2219/21138 , G05B2219/23277 , G05B2219/23371 , G05B2219/24125 , G05B2219/25243 , G05B2219/25301 , G05B2219/25341 , G05B2219/25435 , G05B2219/25451 , G05B2219/2637 , G06F12/0802 , Y02T10/47
摘要： A control unit for vehicle is provided where an increase in a number of input/output and upgrading functions can easily be performed and, in addition to this, changing of a program in a control unit can easily be performed even when a single-chip micro-computer is used. A control unit is constructed such as to comprise an interface software memory storing an interface software program for connecting an application software program with an operating system in an internal ROM, a CPU for performing computation of the application software program and the interface software program, a RAM storing data such as the result of the computation, an I/O unit for extending the control unit, and an extending device for communicating memory data through a bus or a LAN. A single-chip micro-computer used in vehicle control can easily cope with an increase in the input/output ports or additional functions, and an application software program can continuously be used only by rewriting an interface software program. Further, re-manufacturing of a core unit is unnecessary. Therefore, development of a control unit including programs becomes easy.
摘要翻译：提供了一种用于车辆的控制单元，其中可以容易地执行输入/输出和升级功能的数量的增加，并且除此之外，即使当单片微处理器也可以容易地执行控制单元中的程序的改变 - 使用计算机。控制单元被构造为包括存储用于将应用软件程序与内部ROM中的操作系统连接的接口软件程序的接口软件存储器，用于执行应用软件程序和接口软件程序的计算的CPU，存储诸如计算结果的数据的RAM，用于扩展控制单元的I / O单元，以及用于通过总线或LAN传送存储器数据的扩展装置。用于车辆控制的单片微型计算机可以容易地应对输入/输出端口的增加或附加功能，并且应用软件程序可以仅通过重写接口软件程序来连续使用。此外，不需要重新制造核心单元。因此，包含程序的控制单元的开发变得容易。

35. 发明授权

US5349351A Analog-digital converting device 失效
标题翻译：模拟数字转换器
公开(公告)号：US5349351A
公开(公告)日：1994-09-20
申请号：US940332
申请日：1992-09-03
申请人： Sanshiro Obara , Mitsuru Watabe , Rika Minami , Shigeki Morinaga
发明人： Sanshiro Obara , Mitsuru Watabe , Rika Minami , Shigeki Morinaga
IPC分类号： G01R19/00 , G06F15/78 , H02M7/48 , H03M1/12 , G05B11/28
CPC分类号： H03M1/1225
摘要： An analog-digital converting device is designed such that when an operation of converting a special analog signal into a digital signal and an operation of converting another analog signal into a digital signal are instructed concurrently, priority is given to the conversion operation of the special analog signal, The analog-digital converting device includes an analog multiplexer having a main channel and a sub channel, a sample holder, an AD converter, a conversion result register having a plurality of storage areas, and an AD control circuit for controlling the drive of the individual components according to an instruction of a CPU. When the analog signals input to the channels are converted into digital signals in sequence, priority is given to AD conversion of the analog signal input to the main channel over AD conversion of the analog signal input to the sub channel.
摘要翻译：模拟数字转换装置被设计成当同时指示将特殊模拟信号转换为数字信号的操作和将另一个模拟信号转换为数字信号的操作时，优先考虑特殊模拟信号的转换操作模拟数字转换装置包括具有主信道和子信道的模拟多路复用器，样本保持器，AD转换器，具有多个存储区域的转换结果寄存器，以及用于控制驱动器的AD控制电路各个组件根据CPU的指令。当输入到通道的模拟信号按顺序转换为数字信号时，通过AD转换将模拟信号输入到主通道的模拟信号的AD转换优先给输入到子通道。

36. 发明授权

US5293558A Multiplication, division and square root extraction apparatus 失效
标题翻译：乘法，除法和平方根提取仪
公开(公告)号：US5293558A
公开(公告)日：1994-03-08
申请号：US536565
申请日：1990-07-03
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
IPC分类号： G06F7/52 , G06F7/552 , G06F7/57 , G06F7/38
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译： PCT No.PCT / JP89 / 01134 Sec。 371日期1990年7月3日 102（e）日期1990年7月3日PCT提交1989年11月2日PCT公布。出版物WO90 / 05335 日期1990年5月17日。一种乘法，除法和平方根提取装置，其通过使用迭代近似来计算加法，除法和平方根提取函数的解，具有连接到a的规定位宽的乘法器，加法器 - 减法器和移位器总线。通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。

37. 发明授权

US5125095A System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus 失效
标题翻译：在多协处理器装置中使用微处理器地址线进行协处理器选择的系统
公开(公告)号：US5125095A
公开(公告)日：1992-06-23
申请号：US678906
申请日：1991-03-28
申请人： Takuichiro Nakazawa , Makoto Hanawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki , Shigeki Morinaga , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
发明人： Takuichiro Nakazawa , Makoto Hanawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki , Shigeki Morinaga , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
IPC分类号： G06F9/38 , G06F15/16 , G06F15/177
CPC分类号： G06F9/3877 , G06F9/3885
摘要： A microcomputer system has a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor. An address bus and a data bus interconnect the coprocessors with the microprocessor. The microprocessor sends instruction data to the coprocessors via the data bus and concurrently sends coprocessor designation data to the coprocessors via the address bus. The coprocessor designated by the designation data reads and reacts to the instruction data while the other coprocessors within the system disregard the instruction data.
摘要翻译：微计算机系统具有微处理器和多个独立的协处理器，用于根据从微处理器发送的指令数据执行各个指令。地址总线和数据总线将协处理器与微处理器互连。微处理器通过数据总线向协处理器发送指令数据，同时通过地址总线向协处理器发送协处理器指定数据。由指定数据指定的协处理器读取并对指令数据进行响应，而系统内的其他协处理器忽略指令数据。

38. 发明授权

US5023924A Speed control apparatus for movable equipment 失效
标题翻译：移动设备调速装置
公开(公告)号：US5023924A
公开(公告)日：1991-06-11
申请号：US473915
申请日：1990-02-02
申请人： Fumio Tajima , Hiroshi Katayama , Kunio Miyashita , Shigeki Morinaga , Seiichi Narushima
发明人： Fumio Tajima , Hiroshi Katayama , Kunio Miyashita , Shigeki Morinaga , Seiichi Narushima
IPC分类号： H02P6/00 , H02P6/06 , H02P6/10
CPC分类号： H02P6/10 , H02P6/006 , H02P6/06 , Y10S388/906
摘要： In order to provide a speed control apparatus for a movable equipment having small torque ripples and speed variation, the present invention has a speed control means which comprises a driver for providing a current or a voltage having a magnitude corresponding to the instructed speed, a speed detection circuit for detecting a speed on the basis of a signal from the speed detector and a microcomputer for driving the driver by comparing the speed instruction signal with a speed signal obtained from the speed detection circuit. The microcomputer includes a harmonic wave component detecting means for detecting a harmonic wave component contained in a speed variation mode which is obtained from the speed detection circuit and has a function of making the gain of a speed control system variable by the harmonic wave component detected by the harmonic wave component detecting means.

39. 再颁专利

USRE32163E Error preventing device for an electronic engine control apparatus 失效
标题翻译：用于电子发动机控制装置的错误防止装置
公开(公告)号：USRE32163E
公开(公告)日：1986-05-27
申请号：US511590
申请日：1983-07-07
申请人： Hiroastu Tokuda , Shigeki Morinaga , Hideo Nakamura
发明人： Hiroastu Tokuda , Shigeki Morinaga , Hideo Nakamura
IPC分类号： F02D41/34 , F02D21/08 , F02D41/26 , F02D45/00 , F02P5/15 , F02P15/00 , G05B15/02
CPC分类号： F02P5/1504 , F02D41/26 , F02P15/006 , Y02T10/46
摘要： An electronic control apparatus includes a digital processor which receives data from sensors indicating conditions of the engine and supplies output control data for operating various actuators which control the engine operation. The interfacing of data between the sensors, the digital processor and the actuators is effected through a set of registers and a controlled incrementing device. The set of registers includes a plurality of reference registers which store engine control data supplied from the digital processor. Another set of registers store respective sets of codes the values of which are sequentially and selectively incremented in accordance with a prescribed timing signal pattern during the rotation of the engine crankshaft. The data in these respective registers are compared with one another and upon the contents of a register, the contents of which are incremented by the timing signal pattern reaching the value stored in the reference register the data contained in which is supplied from the digital processor, an output is supplied to operate a respective engine actuator. Since the data supplied by the digital processor may vary at any time depending upon operating conditions, which are supplied by the digital processor, are not fixed but are subject to variation. If, at the time the digital processor is modifying or changing, namely updating, the data contained in a reference register, the value in a corresponding one of the second set of registers becomes equal to the old data with which it has been compared, no output signal is permitted to be supplied to an engine actuator until after the new data supplied by the digital processor has been input to the appropriate reference register. This preventing or inhibiting action enables the system to control the engine actuators in an extremely accurate manner, as the reference data upon which actuator control signals are ultimately based is always permitted to be dynamically updated so that the engine is always controlled on the basis of current engine conditions.

40. 再颁专利

USRE32140E Electronic engine control apparatus 失效
标题翻译：电子发动机控制装置
公开(公告)号：USRE32140E
公开(公告)日：1986-05-06
申请号：US509769
申请日：1983-06-30
申请人： Hiroastu Tokuda , Shigeki Morinaga , Hideo Nakamura
发明人： Hiroastu Tokuda , Shigeki Morinaga , Hideo Nakamura
IPC分类号： F02D21/08 , F02D41/24 , F02M25/07 , F02P5/15
CPC分类号： F02D41/0077 , F02D41/28 , F02P5/1502 , F02D2041/2027 , F02M26/53 , Y02T10/46 , Y02T10/47
摘要： An electronic engine control apparatus in which the timing of the ignition and the fuel injection are calculated from a negative pressure in the intake manifold of the engine or the flow rate of suction air and the rotational speed of the engine. A reference register group is constituted of registers for storing the result of the calculation while an instantaneous register group is made up of registers for storing the instantaneous states of actuators. One of the registers of the reference register group and one of the registers of the instantaneous register group are selected according to a stage timing signal so that the contents of the two registers selected are compared with each other.

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