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31. 发明授权

US07580275B2 Control of a memory matrix with resistance hysteresis elements 有权
标题翻译：具有电阻滞后元件的存储矩阵的控制
公开(公告)号：US07580275B2
公开(公告)日：2009-08-25
申请号：US11817754
申请日：2006-03-03
申请人： Teunis Jan Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
发明人： Teunis Jan Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2213/72
摘要： A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.
摘要翻译：使用用于存储矩阵的控制电路（1,11），其定义了在至少两个空闲电路状态，全列更新电路状态和列选择性更新状态之间使用电路状态转换的写入处理。在第二个在访问期间，控制电路在执行列选择性更新命令期间从第一空闲状态（II）来回切换到列选择性更新状态（W），并且从列选择性更新状态（E）到在执行全部列更新命令期间的第二空闲状态（12）。控制电路（1,11）被保持在第一和第二空闲状态（II，12）中，而在连续列选择性更新命令的执行和所有列更新命令之间没有切换到第二和第一空闲状态（12，II）分别。

32. 发明申请

US20080316805A1 Electronic Circuit With a Memory Matrix 有权
标题翻译：具有存储矩阵的电子电路
公开(公告)号：US20080316805A1
公开(公告)日：2008-12-25
申请号：US12096226
申请日：2006-12-04
申请人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
发明人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C17/16 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/2454 , H01L27/2472
摘要： An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.
摘要翻译：电子电路包括具有存储单元（16）的行和列的存储矩阵（60）。为每行设置第一行导体（10,12）。提供第二行导体（12）用于连续重叠相邻行对。为每个列提供列导体（14）。每个存储器单元（16）包括存取晶体管（160），节点（166）和第一和第二电阻性存储元件（162,164）。存取晶体管（160）优选地是具有耦合到存储单元（16）的行的第一行导体（10）的控制电极的垂直晶体管，耦合在用于列的列导体（14）之间的主电流通道的存储单元（160）和节点（166）。第一和第二电阻性存储器元件（162,164）耦合在存储器单元所属的行对之间的节点（166）和第二行导体（12）之间。

33. 发明授权

US07232734B2 Radiation emitting semiconductor device and method of manufacturing such a device 失效
公开(公告)号：US07232734B2
公开(公告)日：2007-06-19
申请号：US10534385
申请日：2003-10-31
申请人： Pierre Hermanus Woerlee , Gert Wim 'T Hooft , Jisk Holleman
发明人： Pierre Hermanus Woerlee , Gert Wim 'T Hooft , Jisk Holleman
IPC分类号： H01L21/331
CPC分类号： H01L33/34 , H01L27/15
摘要： Radiation-emitting semiconductor device and method of manufacturing such a device. The invention relates to a radiation-emitting semiconductor device (10) comprising a silicon-containing semiconductor body (1) and a substrate (2), which semiconductor body (1) comprises a lateral semiconductor diode positioned on an insulating layer (7) which separates the diode from the substrate (2). The lateral semiconductor diode comprises a first semiconductor region (3) of a first conductivity type and with a first doping concentration, a second semiconductor region (4) of the first or a second conductivity type opposite to the first conductivity type and with a second doping concentration which is lower than the first doping concentration, and a third semiconductor region (5) of the second conductivity type and with a third doping concentration which is higher than the second doping concentration, the first and the third region (3, 5) each being provided with a connection region (6, 8), and, during operation, radiation (S) being generated in the second region (4) due to recombination of charge carriers injected therein from the first and the third region (3, 5). According to the invention, the second semiconductor region (4) comprises a central part (4A) which is surrounded by a further part (4B) the bandgap of which is larger than the bandgap of the central part (4A). In this way, the radiation yield is increased in an indirect semiconductor material such as silicon in the central part (4A) as translation of the relatively long-living charge carriers towards a non-radiative recombination center is limited because of the barriers in the valence and conduction band in the further part (4B). Preferably, the bandgap in the further part (4B) is made larger in that the thickness of said part (4B) is so small that quantum size effects occur therein, while the central part (4A) has a thickness which is so large that such effects do not occur or substantially do not occur.

34. 发明申请

US20120165853A1 Femoral Vein Catheter for Improving Cardiac Output, Drug Delivery and Automated CPR Optimization 审中-公开
标题翻译：股静脉导管改善心脏输出，药物输送和自动CPR优化
公开(公告)号：US20120165853A1
公开(公告)日：2012-06-28
申请号：US13392602
申请日：2010-09-09
申请人： Igor Wilhelmus Franciscus Paulussen , Pierre Hermanus Woerlee , Gerrit Jan Noordergraaf , Abraham Noordergraaf
发明人： Igor Wilhelmus Franciscus Paulussen , Pierre Hermanus Woerlee , Gerrit Jan Noordergraaf , Abraham Noordergraaf
IPC分类号： A61M29/00
CPC分类号： A61B17/12136 , A61B5/14503 , A61B5/14542 , A61B5/14546 , A61B17/12036 , A61B17/12109 , A61B2017/00022 , A61F2/24 , A61F2/2475 , A61M2025/0002 , A61M2025/1052
摘要： A blood flow control device, comprising a flow influencing element arranged to be placed in the vena cava of a human during cardiopulmonary resuscitation and controllable between a non-to-low-flow state in which the flow influencing element substantially reduces a blood flow within the vena cava, and a flow state, in which the flow influencing element allows substantially unreduced blood flow, responsive to an existing or a predicted pressure difference between an upstream area and a downstream area of the flow influencing element. The blood flow control device is capable of reducing retrograde blood flow during the compression phase of CPR and thus improves the efficiency of CPR and blood perfusion. The blood flow control device can also be used for the administration of drugs almost directly to the heart, as well as for measuring physiological and chemical properties, such as blood gases.
摘要翻译：一种血流控制装置，包括流量影响元件，其被布置成在心肺复苏期间放置在人的腔静脉中并且可在非流动状态之间控制，其中流动影响元件基本上减少了血液流量流动状态，其中流动影响元件响应于流动影响元件的上游区域和下游区域之间的现有或预测的压力差，允许基本上未减少的血流量。血流控制装置能够在CPR的压缩阶段减少逆行血流，从而提高CPR和血液灌注的效率。血液流量控制装置也可用于几乎直接向心脏施用药物，以及用于测量生理和化学性质，例如血液气体。

35. 发明申请

US20120052470A1 CPR DUMMY WITH AN ACTIVE MECHANICAL LOAD 审中-公开
标题翻译： CPR具有主动机械负载
公开(公告)号：US20120052470A1
公开(公告)日：2012-03-01
申请号：US13320222
申请日：2010-04-29
申请人： Pierre Hermanus Woerlee , Igor Wilhelmus Franciscus Paulussen , Frank Titus Marie Jaartsveld
发明人： Pierre Hermanus Woerlee , Igor Wilhelmus Franciscus Paulussen , Frank Titus Marie Jaartsveld
IPC分类号： G09B23/28
CPC分类号： G09B23/288
摘要： A cardiopulmonary resuscitation (CPR) simulation load capable of simulating a reactive force of a patient's chest upon chest depression, the cardiopulmonary resuscitation simulation load comprising an active actuator (M) arranged to generate at least part of the reactive force, and a controller (CTRL) arranged to provide a control signal to the active actuator. A CPR simulation manikin comprising such a CPR simulation load is also proposed. Furthermore, a method for simulating a reactive force of a patient's chest during cardiopulmonary resuscitation by means of a simulation manikin, the method comprising: measuring a depression of a simulation manikin chest; calculating a resulting reactive force depending on the measured depression of the simulation manikin chest; applying the resulting reactive force to the patient's chest by means of an active actuator. With an active actuator the simulated reactive force may be more easily adjusted and the non-linear behavior of a true patient's chest can be accurately modeled.
摘要翻译：一种心肺复苏（CPR）模拟负载，其能够模拟患者胸部在胸部下压时的反作用力，所述心肺复苏模拟载荷包括布置成产生至少部分反作用力的主动致动器（M）和控制器（CTRL ），其被布置成向主动致动器提供控制信号。还提出了包括这样的CPR模拟负载的CPR模拟人体模型。此外，一种用于通过模拟人体模型来模拟患者胸部在心肺复苏期间的反作用力的方法，所述方法包括：测量模拟人体模型胸部的凹陷; 根据模拟人体模型胸部的测量下降计算产生的反作用力; 通过主动执行器将所产生的反作用力施加到患者的胸部。使用主动执行器，可以更容易地调整模拟的反作用力，并且可以精确地建模真实患者胸部的非线性行为。

36. 发明授权

US07834668B2 Single threshold and single conductivity type amplifier/buffer 有权
标题翻译：单阈值和单导电型放大器/缓冲器
公开(公告)号：US07834668B2
公开(公告)日：2010-11-16
申请号：US12088735
申请日：2006-10-04
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03B1/00
CPC分类号： H03K19/01721 , H03K19/09441
摘要： An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.
摘要翻译：由单阈值和单导电类型的电路元件组成的放大器/缓冲器，包括用于接收用于缓冲/放大的一个或多个输入的输入级，并且提供中间级以控制放大器/缓冲器的输出。中间信号被提供给升压电路，该升压电路被配置为当所述信号超过预定值时升高所述信号。放大器/缓冲器还具有用于至少接收所述信号并提供放大/缓冲输出的输出级。

37. 发明授权

US07671660B2 Single threshold and single conductivity type logic 有权
标题翻译：单阈值和单导电类型逻辑
公开(公告)号：US07671660B2
公开(公告)日：2010-03-02
申请号：US12067075
申请日：2006-09-14
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03K17/16
CPC分类号： H03K19/017 , H03K19/096
摘要： A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current paths being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400). It further includes a bootstrapping circuit (422) for enabling an additional supply of charge to a first end of said capacitive means, resulting in a boosted voltage at a second end of said capacitive means.
摘要翻译：逻辑组件（400）由单个阈值和单导电类型的电路元件组成，并且包括具有至少一组开关的逻辑电路（410），每组开关各自具有主电流路径和控制端子。主电流路径形成具有耦合到电源线的第一和第二导电端子的串联装置。主电流路径耦合到形成逻辑组件（400）的输出的公共节点。所述开关的控制端耦合到时钟电路，用于向所述控制端提供相互不重叠的时钟信号。逻辑组件还包括用于升压所述逻辑组件（400）的输出的输出升压电路（420），包括用于使能向所述逻辑组件（400）的输出提供附加电荷的电容装置（421）。它还包括一个自举电路（422），用于使得能够向所述电容性装置的第一端额外提供电荷，导致在所述电容装置的第二端处的升压电压。

38. 发明申请

US20090200536A1 Method for manufacturing an electric device with a layer of conductive material contracted by nanowire 有权
标题翻译：制造具有由纳米线收缩的导电材料层的电气装置的方法
公开(公告)号：US20090200536A1
公开(公告)日：2009-08-13
申请号：US11631212
申请日：2005-06-28
申请人： Robertus Theodorus Franciscus Van Schaijk , Prabhat Agarwal , Erik Petrus Antonius Maria Bakkers , Martijn Henri Richard Lankhorst , Michiel Jos Van Duuren , Abraham Rudolf Balkenende , Louis Felix Feiner , Pierre Hermanus Woerlee
发明人： Robertus Theodorus Franciscus Van Schaijk , Prabhat Agarwal , Erik Petrus Antonius Maria Bakkers , Martijn Henri Richard Lankhorst , Michiel Jos Van Duuren , Abraham Rudolf Balkenende , Louis Felix Feiner , Pierre Hermanus Woerlee
IPC分类号： H01L47/00 , H01L21/3205
CPC分类号： H01L45/1273 , B82Y10/00 , G11C13/0004 , G11C13/025 , G11C2213/81 , H01L21/28525 , H01L21/76879 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/16
摘要： The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW) electrically connecting a first terminal (172) of the electric device and the layer (107) of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer (107) of memory material to a second terminal (272) of the electric device. Each nanowire (NW) electrically contacts the layer (107) of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device (100) according to the invention.
摘要翻译：根据本发明的电子设备（100）包括存储材料的层（107），其具有可在第一值和第二值之间切换的电阻率。记忆材料可以是相变材料。电气设备（100）还包括电连接电子设备的第一端子（172）和存储器材料层（107）的一组纳米线（NW），从而能够经由纳米线传导来自第一端子的电流（NW）和存储器材料层（107）连接到电气设备的第二端子（272）。每个纳米线（NW）在相应的接触区域中电接触存储器材料的层（107）。所有接触区域基本相同。根据本发明的方法适用于制造根据本发明的电子设备（100）。

39. 发明申请

US20090129190A1 DRIVING A MEMORY MATRIX OF RESISTANCE HYSTERESIS ELEMENTS 有权
标题翻译：驱动电阻HYSTERESIS元件的记忆矩阵
公开(公告)号：US20090129190A1
公开(公告)日：2009-05-21
申请号：US11817715
申请日：2006-02-28
申请人： Teunis Jian Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
发明人： Teunis Jian Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
IPC分类号： G11C7/00 , G11C11/416 , G11C8/00 , G11C5/14
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0028 , G11C2213/15 , G11C2213/72
摘要： A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity. Furthermore voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform write actions. The voltage differences for the write actions have a write polarity corresponding to the smaller hysteresis threshold, for updating cells (20) that are selected dependent on write data.
摘要翻译：存储器矩阵（10）包括单元的行和列，每个单元包括串联耦合在单元（20）的行端子和列端子之间的电阻滞后元件（24）和阈值元件（22）。电阻滞后元件（24）分别具有相互相反极性的相互较大和较小的滞后阈值。在所选行中的列端子和单元（20）的行端子之间施加电压差，以便执行读取动作。这些电压差具有读取极性，使得电池（20）两端的电压处于对应于较大滞后阈值的方向。电压差被施加在所选列的单元（20）的列端子和行端子之间，以便执行擦除动作，所选行的所有单元（20）在擦除动作中被共同擦除。擦除动作的电压差具有读极性。此外，在列端子和选定行中的单元（20）的行端子之间施加电压差，以便执行写入动作。写入动作的电压差具有对应于较小滞后阈值的写入极性，用于更新根据写入数据选择的单元（20）。

40. 发明申请

US20090122590A1 CONTROL OF A MEMORY MATRIX WITH RESISTANCE HYSTERESIS ELEMENTS 有权
标题翻译：具有电阻HYSTERESIS元件的记忆矩阵的控制
公开(公告)号：US20090122590A1
公开(公告)日：2009-05-14
申请号：US11817754
申请日：2006-03-03
申请人： Teunis Jan Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
发明人： Teunis Jan Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
IPC分类号： G11C11/00 , G11C8/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2213/72
摘要： A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.
摘要翻译：使用用于存储矩阵的控制电路（1,11），其定义了在至少两个空闲电路状态，全列更新电路状态和列选择性更新状态之间使用电路状态转换的写入处理。在第二个在访问期间，控制电路在执行列选择性更新命令期间从第一空闲状态（II）来回切换到列选择性更新状态（W），并且从列选择性更新状态（E）到在执行全部列更新命令期间的第二空闲状态（12）。控制电路（1,11）被保持在第一和第二空闲状态（II，12）中，而在连续列选择性更新命令的执行和所有列更新命令之间没有切换到第二和第一空闲状态（12，II）分别。

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