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31. 发明授权

US07372736B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07372736B2
公开(公告)日：2008-05-13
申请号：US11391662
申请日：2006-03-28
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04 , H01L29/76 , H01L23/544
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
摘要翻译：非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

32. 发明授权

US07369438B2 Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications 有权
标题翻译：多功能java卡，SIM卡，生物护照和生物识别卡应用的组合内存设计和技术
公开(公告)号：US07369438B2
公开(公告)日：2008-05-06
申请号：US11305700
申请日：2005-12-16
申请人： Peter W. Lee
发明人： Peter W. Lee
IPC分类号： G11C11/34
CPC分类号： G11C11/005 , G11C16/0408 , G11C16/0483 , G11C17/12 , H01L27/115 , H01L29/0646 , H01L29/7885
摘要： A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile memory arrays have address space associated with each other such that each array may be addressed with common addressing signals. The combination volatile and nonvolatile memory integrated circuit further has a memory control circuit in communication with external circuitry to receive address, command, and data signals. The memory control circuit interprets the address, command, and data signals, and for transfer to the volatile memory array and the nonvolatile memory arrays for reading, writing, programming, and erasing the volatile and nonvolatile memory arrays. The volatile memory array is may be a SRAM, a pseudo SRAM, or a DRAM. Any of the nonvolatile memory arrays maybe masked programmed ROM arrays, NAND configured flash memory NAND configured EEPROM.
摘要翻译：易失性和非易失性存储器集成电路的组合具有放置在基板和多个非易失性存储器阵列上的至少一个易失性存储器阵列。易失性和非易失性存储器阵列具有彼此相关联的地址空间，使得每个阵列可以用公共寻址信号寻址。组合易失性和非易失性存储器集成电路还具有与外部电路通信的存储器控制电路，以接收地址，命令和数据信号。存储器控制电路解释地址，命令和数据信号，并且用于传送到易失性存储器阵列和用于读取，写入，编程和擦除易失性和非易失性存储器阵列的非易失性存储器阵列。易失性存储器阵列可以是SRAM，伪SRAM或DRAM。任何非易失性存储器阵列都可以屏蔽编程的ROM阵列，NAND配置闪存NAND配置的EEPROM。

33. 发明授权

US07120064B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
公开(公告)号：US07120064B2
公开(公告)日：2006-10-10
申请号：US11036961
申请日：2005-01-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

34. 发明授权

US07102929B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07102929B2
公开(公告)日：2006-09-05
申请号：US11036835
申请日：2005-01-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

35. 发明授权

US07064978B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07064978B2
公开(公告)日：2006-06-20
申请号：US10351180
申请日：2003-01-24
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04 , H01L29/76 , H01L23/544
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
摘要翻译：非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

36. 发明授权

US06891221B2 Array architecture and process flow of nonvolatile memory devices for mass storage applications 有权
标题翻译：用于大容量存储应用的非易失性存储器件的阵列架构和处理流程
公开(公告)号：US06891221B2
公开(公告)日：2005-05-10
申请号：US10790578
申请日：2004-03-01
申请人： Peter W. Lee , Hung-Sheng Chen , Vei-Han Chan
发明人： Peter W. Lee , Hung-Sheng Chen , Vei-Han Chan
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0491 , H01L27/115
摘要： In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.
摘要翻译：在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。通过使用Fowler-Nordheim从浮置栅极到控制栅极的隧道，通过在浮栅的壁上形成的多晶硅氧化物来消除电池。

37. 发明授权

US06717846B1 Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground configuration 有权
标题翻译：具有镜像在虚拟接地配置中的分离门存储器单元的非易失性半导体存储器
公开(公告)号：US06717846B1
公开(公告)日：2004-04-06
申请号：US09696085
申请日：2000-10-26
申请人： Peter W. Lee , Hung-Sheng Chen , Vei-Han Chan
发明人： Peter W. Lee , Hung-Sheng Chen , Vei-Han Chan
IPC分类号： G11C1616
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0491 , H01L27/115
摘要： In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. The cells are crased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.
摘要翻译：在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。使用Fowler-Nordheim，通过在浮栅的壁上形成的多晶硅氧化物，利用Fowler-Nordheim将浮动栅极的电子隧穿到控制栅极进行电池堆积。

38. 发明授权

US06563742B1 Method to turn a flash memory into a versatile, low-cost multiple time programmable EPROM 有权
标题翻译：将闪存转换成多功能，低成本多时间可编程EPROM的方法
公开(公告)号：US06563742B1
公开(公告)日：2003-05-13
申请号：US10090356
申请日：2002-03-04
申请人： Peter W. Lee , Tam H. Tran
发明人： Peter W. Lee , Tam H. Tran
IPC分类号： G11C1600
CPC分类号： G11C16/3409 , G11C16/0408 , G11C16/16 , G11C16/3404 , G11C16/344 , G11C16/3445
摘要： A multiple time programmable (MTP) memory device is achieved. The device comprises, first, a memory cell array including a means of electrical erasability and electrical programmability. The memory cell array comprises, preferably, a Flash memory cell array. A package has an external pin configuration that conforms to the JEDEC standard for an EPROM device wherein an external, positive programming voltage (VPP) pin is provided. Finally, an external, negative erasing voltage (VNN) pin is provided. The VNN pin is, preferably, multiplexed with the chip enable bar (CEB) pin.
摘要翻译：实现了多时间可编程（MTP）存储器件。该装置首先包括一个包括电可擦除性和电可编程性的装置的存储单元阵列。存储单元阵列优选地包括闪存单元阵列。封装具有符合EPROM器件的JEDEC标准的外部引脚配置，其中提供外部正的编程电压（VPP）引脚。最后，提供一个外部负的擦除电压（VNN）引脚。 VNN引脚优选地与芯片使能条（CEB）引脚复用。

39. 发明授权

US06319324B1 Method and apparatus for elimination of TEOS/ozone silicon oxide surface sensitivity 失效
标题翻译：消除TEOS /臭氧氧化硅表面灵敏度的方法和装置
公开(公告)号：US06319324B1
公开(公告)日：2001-11-20
申请号：US09662248
申请日：2000-09-14
申请人： Bang C. Nguyen , Shankar Vankataranan , Ruby Liao , Peter W. Lee
发明人： Bang C. Nguyen , Shankar Vankataranan , Ruby Liao , Peter W. Lee
IPC分类号： C23C1600
CPC分类号： H01L21/02271 , C23C16/0272 , C23C16/402 , C23C16/45557 , H01L21/02164 , H01L21/02304 , H01L21/31612
摘要： A method and apparatus for reducing surface sensitivity of a TEOS/O3 SACVD silicon oxide layer, formed over a substrate, that deposits a ramp layer while ramping pressure to a target deposition pressure and deposits an SACVD layer over the ramp layer. In one embodiment, the flow of ozone is stopped during the pressure ramp-up to control the thickness of the ramp layer.
摘要翻译：一种用于降低在衬底上形成的TEOS / O 3 SACVD氧化硅层的表面灵敏度的方法和装置，其沉积斜坡层，同时将压力升高到目标沉积压力，并在斜坡层上沉积SACVD层。在一个实施例中，在压力升高期间停止臭氧流以控制斜坡层的厚度。

40. 再颁专利

USRE37419E1 Flash memory array and decoding architecture 有权
标题翻译：闪存阵列和解码架构
公开(公告)号：USRE37419E1
公开(公告)日：2001-10-23
申请号：US09430060
申请日：1999-10-29
申请人： Fu-Change Hsu , Hsing-Ya Tsao , Peter W. Lee
发明人： Fu-Change Hsu , Hsing-Ya Tsao , Peter W. Lee
IPC分类号： G11C1604
CPC分类号： G11C11/5621 , G11C8/14 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3445 , G11C2211/5621 , H01L27/115
摘要： A flash memory circuit includes a word line decoder with even and odd word line latches and a source line decoder with a source line latch. The word line decoders and the source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and a verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that may be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments and having segmented source lines controlled by source segment control lines and transistors, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing. Several different approaches are presented for the layout of source segment control lines and transistors as well as the word lines.
摘要翻译：闪存电路包括具有偶数和奇数字线锁存器的字线解码器和具有源极线锁存器的源极线解码器。字线解码器和源极线解码器提供同时擦除闪存中的两个相邻字线的存储单元的能力，并且逐字地验证存储单元字。通过同时擦除两个相邻行，本发明的实施例消除了与常规闪存电路相关的过度擦除和源干扰问题。解码架构提供了可能从一对到大量多对字线的灵活的擦除大小。通过将字线的存储单元划分成多个段并具有由源段控制线和晶体管控制的分段源极线，解码电路还提供选择用于擦除的字线段的存储单元的能力。对于源段控制线和晶体管以及字线的布局提出了几种不同的方法。

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