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31. 发明申请

US20100051474A1 METHOD AND COMPOSITION FOR ELECTRO-CHEMICAL-MECHANICAL POLISHING 审中-公开
标题翻译：电化学机械抛光方法与组合
公开(公告)号：US20100051474A1
公开(公告)日：2010-03-04
申请号：US12548893
申请日：2009-08-27
申请人： Panayotis C. Andricacos , Caliopi Andricacos , Donald F. Canaperi , Emanuel I. Cooper , John M. Cotte , Hariklia Deligianni , Laertis Economikos , Daniel C. Edelstein , Silvia Franz , Balasubramanian Pranatharthiharan , Mahadevaiyer Krishnan , Andrew P. Mansson , Erick G. Walton , Alan C. West
发明人： Panayotis C. Andricacos , Caliopi Andricacos , Donald F. Canaperi , Emanuel I. Cooper , John M. Cotte , Hariklia Deligianni , Laertis Economikos , Daniel C. Edelstein , Silvia Franz , Balasubramanian Pranatharthiharan , Mahadevaiyer Krishnan , Andrew P. Mansson , Erick G. Walton , Alan C. West
IPC分类号： B23H5/06
CPC分类号： C25F3/02 , B23H5/08 , C09G1/04 , H01L21/32125
摘要： Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.
摘要翻译：提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

32. 发明授权

US07615482B2 Structure and method for porous SiCOH dielectric layers and adhesion promoting or etch stop layers having increased interfacial and mechanical strength 有权
标题翻译：多孔SiCOH介电层的结构和方法以及具有增加的界面和机械强度的粘合促进或蚀刻停止层
公开(公告)号：US07615482B2
公开(公告)日：2009-11-10
申请号：US11690248
申请日：2007-03-23
申请人： Daniel C. Edelstein , Alexandros Demos , Stephen M. Gates , Alfred Grill , Steven E. Molis , Vu Ngoc Tran Nguyen , Steven Reiter , Darryl D. Restaino , Kang Sub Yim
发明人： Daniel C. Edelstein , Alexandros Demos , Stephen M. Gates , Alfred Grill , Steven E. Molis , Vu Ngoc Tran Nguyen , Steven Reiter , Darryl D. Restaino , Kang Sub Yim
IPC分类号： H01L21/4763
CPC分类号： C23C16/401 , C23C16/0272 , C23C16/029 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/31695 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L2221/1047 , Y10T428/24851 , Y10T428/249961
摘要： Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductive material, the oxide layer having essentially no carbon, a graded transition layer on the oxide layer, the graded transition layer having essentially no carbon at the interface with the oxide layer and gradually increasing carbon towards a porous SiCOH layer, and a porous SiCOH (pSiCOH) layer on the graded transition layer, the porous pSiCOH layer having an homogeneous composition throughout the layer. The method includes a process wherein in the graded transition layer, there are no peaks in the carbon concentration and no dips in the oxygen concentration.
摘要翻译：公开了一种用于形成包括具有增加的机械强度的SiCOH层的结构的结构和方法。该结构包括具有电介质或导电材料层的基底，介电层或导电材料层上的氧化物层，氧化物层基本上不含碳，氧化物层上的渐变过渡层，梯度过渡层基本上在与氧化物层的界面处没有碳并逐渐向多孔SiCOH层增加碳，并且在渐变过渡层上的多孔SiCOH（pSiCOH）层，多孔pSiCOH层在整个层中具有均匀的组成。该方法包括一种方法，其中在渐变过渡层中，在碳浓度中没有峰，而在氧浓度中没有下降。

33. 发明授权

US07585722B2 Integrated circuit comb capacitor 有权
标题翻译：集成电路梳状电容
公开(公告)号：US07585722B2
公开(公告)日：2009-09-08
申请号：US11306746
申请日：2006-01-10
申请人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
发明人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L28/87 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.
摘要翻译：本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

34. 发明申请

US20090200636A1 SUB-LITHOGRAPHIC DIMENSIONED AIR GAP FORMATION AND RELATED STRUCTURE 有权
标题翻译：亚平面尺寸空气隙形成和相关结构
公开(公告)号：US20090200636A1
公开(公告)日：2009-08-13
申请号：US12029800
申请日：2008-02-12
申请人： Daniel C. Edelstein , Nicholas C. M. Fuller , David V. Horak , Elbert E. Huang , Wai-Kin Li , Anthony D. Lisi , Satyanarayana V. Nitta , Shom Ponoth
发明人： Daniel C. Edelstein , Nicholas C. M. Fuller , David V. Horak , Elbert E. Huang , Wai-Kin Li , Anthony D. Lisi , Satyanarayana V. Nitta , Shom Ponoth
IPC分类号： H01L23/00 , H01L21/4763
CPC分类号： H01L21/7682 , H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.
摘要翻译：公开了亚光刻尺寸气隙形成和相关结构。在一个实施例中，一种方法包括在衬底上形成包括互连的介质层; 在电介质层上沉积盖层; 在所述盖层上沉积光致抗蚀剂; 图案化光致抗蚀剂以包括最多部分地覆盖互连的第一沟槽图案; 在所述第一沟槽图案内形成间隔物以形成具有亚光刻尺寸的第二沟槽图案; 将所述第二沟槽图案转移到所述覆盖层中并进入所述互连之间的所述介电层; 并且通过夹住介电层中的沟槽而沉积另一介质层以形成气隙。

35. 发明申请

US20090140428A1 AIR GAP STRUCTURE HAVING PROTECTIVE METAL SILICIDE PADS ON A METAL FEATURE 有权
标题翻译：在金属特征上具有保护性金属硅化物垫的气隙结构
公开(公告)号：US20090140428A1
公开(公告)日：2009-06-04
申请号：US11949189
申请日：2007-12-03
申请人： Griselda Bonilla , Daniel C. Edelstein , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , David L. Rath , Chih-Chao Yang
发明人： Griselda Bonilla , Daniel C. Edelstein , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , David L. Rath , Chih-Chao Yang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5222 , H01L21/31144 , H01L21/7682 , H01L21/76849 , H01L21/76852 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.
摘要翻译：在包括低k材料层和嵌入其中的金属特征的互连结构上形成硬掩模。将嵌段聚合物施加到硬掩模层上，自组装和图案化以形成聚合物嵌段组分的聚合物基质并且包含圆柱形孔。蚀刻硬掩模和低k材料层以形成空腔。导电材料镀在暴露的金属表面上，包括金属特征的顶表面的部分以形成金属垫。金属硅化物焊盘通过将金属焊盘暴露于含硅气体而形成。进行蚀刻以放大和合并低k材料层中的空腔。通过金属硅化物焊盘防止金属特征被蚀刻。形成具有空隙并且没有金属特征表面的缺陷的互连结构。

36. 发明申请

US20090075472A1 METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS 失效
标题翻译：减轻有机电介质中等离子体损伤的方法
公开(公告)号：US20090075472A1
公开(公告)日：2009-03-19
申请号：US11857760
申请日：2007-09-19
申请人： John C. Arnold , Griselda Bonilla , William J. Cote , Geraud Dubois , Daniel C. Edelstein , Alfred Grill , Elbert Huang , Robert D. Miller , Satya V. Nitta , Sampath Purushothaman , E. Todd Ryan , Muthumanickam Sankarapandian , Terry A. Spooner , Willi Volksen
发明人： John C. Arnold , Griselda Bonilla , William J. Cote , Geraud Dubois , Daniel C. Edelstein , Alfred Grill , Elbert Huang , Robert D. Miller , Satya V. Nitta , Sampath Purushothaman , E. Todd Ryan , Muthumanickam Sankarapandian , Terry A. Spooner , Willi Volksen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/02063 , H01L21/02126 , H01L21/02203 , H01L21/02274 , H01L21/02304 , H01L21/02348 , H01L21/02362 , H01L21/31138 , H01L21/31144 , H01L21/31633 , H01L21/76814 , H01L21/76826 , H01L21/76831
摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.
摘要翻译：提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽用于形成线沟槽和通孔腔的离子蚀刻。减少的线偏压对金属互连结构的电产量具有有益的影响。

37. 发明申请

US20090032959A1 ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS 失效
标题翻译：具有分层尺寸的电熔丝和电阻
公开(公告)号：US20090032959A1
公开(公告)日：2009-02-05
申请号：US11831236
申请日：2007-07-31
申请人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
发明人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L21/76816 , H01L23/5226 , H01L23/5228 , H01L27/101 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a first set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.
摘要翻译：提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。包括导体或半导体的导电结构形成在半导体衬底上。在导电结构上形成至少一个绝缘体层。在所述至少一个绝缘体层中形成凹陷区域。将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

38. 发明申请

US20080296728A1 SEMICONDUCTOR STRUCTURE FOR FUSE AND ANTI-FUSE APPLICATIONS 失效
标题翻译：用于保险丝和抗 - 保险丝应用的半导体结构
公开(公告)号：US20080296728A1
公开(公告)日：2008-12-04
申请号：US11755995
申请日：2007-05-31
申请人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
发明人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.
摘要翻译：提供了一种保险丝/反熔丝结构，其中抗熔丝的编程由邻近熔丝元件形成的电动诱发小丘引起。小丘破裂位于熔丝元件的侧壁上的薄的扩散阻挡层，并且熔丝元件内的导电材料扩散到相邻的介电材料中。保险丝元件包括位于线路开口内的导电材料，该导电材料包括具有第一厚度的第一扩散阻挡层，位于侧壁上的第一厚度和线路开口的底壁。抗熔丝元件包括位于组合的通孔和线路开口内的导电材料，其包括位于组合的通路和线路开口的侧壁上的第一扩散阻挡层和具有大于第二扩散阻挡层的第二厚度的第二扩散阻挡层第一厚度位于第一扩散阻挡层上。

39. 发明申请

US20080173976A1 AIR GAP UNDER ON-CHIP PASSIVE DEVICE 有权
标题翻译：在片上被动设备上的空气隙
公开(公告)号：US20080173976A1
公开(公告)日：2008-07-24
申请号：US11626548
申请日：2007-01-24
申请人： Anthony K. Stamper , Anil K. Chinthakindi , Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , William J. Murphy , Kunal Vaed
发明人： Anthony K. Stamper , Anil K. Chinthakindi , Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , William J. Murphy , Kunal Vaed
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/0688 , H01L21/7682 , H01L23/5222 , H01L23/5227 , H01L23/53295 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.
摘要翻译：提供了一种用于制造微电子芯片的方法，该微电子芯片包括覆盖气隙的诸如电感器的无源器件。在这种方法中，在微电子芯片的半导体区域中形成多个前端（“FEOL”）器件，并且形成多个层叠的层间电介质（“ILD”）层以覆盖多个的多个层叠的ILD层，包括第一ILD层和第二ILD层，其中第二ILD层抵抗攻击第一ILD层的第一蚀刻剂的侵袭。形成无源器件至少覆盖第一ILD层。使用第一蚀刻剂，除去与无源器件对准的第一ILD层的一部分，以形成与被动器件对准的无源器件下方的气隙。

40. 发明申请

US20080164613A1 ULTRA-THIN Cu ALLOY SEED FOR INTERCONNECT APPLICATION 审中-公开
标题翻译：超细铜合金用于互连应用
公开(公告)号：US20080164613A1
公开(公告)日：2008-07-10
申请号：US11621709
申请日：2007-01-10
申请人： Daniel C. Edelstein , Stephen M. Rossnagel
发明人： Daniel C. Edelstein , Stephen M. Rossnagel
IPC分类号： H01L23/48 , H01L21/288
CPC分类号： H01L23/53238 , H01L21/76843 , H01L21/76873 , H01L2924/0002 , H01L2924/00
摘要： A copper interconnection structure which is electroplated onto a silicon layer or semiconductor substrate. The structure includes an ultra-thin copper seed alloy incorporating selectively minor amounts of a dopant material to facilitate a continuous deposition thereof onto the silicon layer or semiconductor substrate. The copper seed alloy may contain dopant material selected from the group of materials consisting of Ru, Ir, Pt, Pd and alloys thereof. Furthermore, there is provided a method for producing the structure.
摘要翻译：电镀在硅层或半导体衬底上的铜互连结构。该结构包括超薄铜种子合金，其选择性地少量掺杂材料，以促进其连续沉积到硅层或半导体衬底上。铜种子合金可以含有选自由Ru，Ir，Pt，Pd及其合金组成的材料组的掺杂剂材料。此外，提供了一种制造该结构的方法。

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