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1. 发明申请

US20080296728A1 SEMICONDUCTOR STRUCTURE FOR FUSE AND ANTI-FUSE APPLICATIONS 失效
标题翻译：用于保险丝和抗 - 保险丝应用的半导体结构
公开(公告)号：US20080296728A1
公开(公告)日：2008-12-04
申请号：US11755995
申请日：2007-05-31
申请人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
发明人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.
摘要翻译：提供了一种保险丝/反熔丝结构，其中抗熔丝的编程由邻近熔丝元件形成的电动诱发小丘引起。小丘破裂位于熔丝元件的侧壁上的薄的扩散阻挡层，并且熔丝元件内的导电材料扩散到相邻的介电材料中。保险丝元件包括位于线路开口内的导电材料，该导电材料包括具有第一厚度的第一扩散阻挡层，位于侧壁上的第一厚度和线路开口的底壁。抗熔丝元件包括位于组合的通孔和线路开口内的导电材料，其包括位于组合的通路和线路开口的侧壁上的第一扩散阻挡层和具有大于第二扩散阻挡层的第二厚度的第二扩散阻挡层第一厚度位于第一扩散阻挡层上。

2. 发明授权

US07572682B2 Semiconductor structure for fuse and anti-fuse applications 失效
标题翻译：保险丝和反熔丝应用的半导体结构
公开(公告)号：US07572682B2
公开(公告)日：2009-08-11
申请号：US11755995
申请日：2007-05-31
申请人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
发明人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.
摘要翻译：提供了一种保险丝/反熔丝结构，其中抗熔丝的编程由邻近熔丝元件形成的电动诱发小丘引起。小丘破裂位于熔丝元件的侧壁上的薄的扩散阻挡层，并且熔丝元件内的导电材料扩散到相邻的介电材料中。保险丝元件包括位于线路开口内的导电材料，该导电材料包括具有第一厚度的第一扩散阻挡层，位于侧壁上的第一厚度和线路开口的底壁。抗熔丝元件包括位于组合的通孔和线路开口内的导电材料，其包括位于组合的通路和线路开口的侧壁上的第一扩散阻挡层和具有大于第二扩散阻挡层的第二厚度的第二扩散阻挡层第一厚度位于第一扩散阻挡层上。

3. 发明授权

US09245794B2 Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application 有权
标题翻译：通过扩散阻挡层和种子层的反应形成合金衬里，用于互连应用
公开(公告)号：US09245794B2
公开(公告)日：2016-01-26
申请号：US13614492
申请日：2012-09-13
申请人： Chih-Chao Yang , Daniel C. Edelstein , Takeshi Nogami
发明人： Chih-Chao Yang , Daniel C. Edelstein , Takeshi Nogami
IPC分类号： H05K1/09 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76846 , H01L21/76844 , H01L21/76858 , H01L21/76867 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , Y10T29/49117 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.
摘要翻译：提供了包括直接位于扩散阻挡层和Cu合金种子层之间的合金衬垫的互连结构以及用于形成这种互连结构的方法。本发明的合金衬垫通过使预先沉积的扩散阻挡金属合金层与覆盖的Cu合金种子层热反应形成。在热反应期间，来自扩散阻挡层和Cu合金种子层的金属合金在扩散阻挡层和Cu籽晶层之间反应形成金属合金反应产物。

4. 发明授权

US08564132B2 Tungsten metallization: structure and fabrication of same 失效
标题翻译：钨金属化：其结构和制造相同
公开(公告)号：US08564132B2
公开(公告)日：2013-10-22
申请号：US13211722
申请日：2011-08-17
申请人： Chih-Chao Yang , Daniel C. Edelstein
发明人： Chih-Chao Yang , Daniel C. Edelstein
IPC分类号： H01L23/482
CPC分类号： H01L21/76838 , H01L21/76814 , H01L21/76831 , H01L21/76849 , H01L21/76856 , H01L21/76867 , H01L21/76885 , H01L21/76895
摘要： A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.
摘要翻译：提供局部互连结构，其中形成在中间线（MOL）电介质材料内的钨区域，即钨柱，在多重互连图案化工艺期间不被损坏和/或污染。这在本公开内容中通过在顶部表面内形成自对准的氮化钨钝化层，并且在钨区域的上侧壁部分之上延伸到包括形成在其中的第一互连图案的MOL介电材料之上。在自对准氮化钨钝化层的形成过程中，还会在MOL介电材料的暴露表面内形成富含氮的电介质表面。然后形成与第一互连图案相邻但不连接的第二布线图案。由于在钨区域上存在自对准的氮化钨钝化层，不会发生钨区域的破坏和/或污染。

5. 发明授权

US08497580B2 Noble metal cap for interconnect structures 有权
标题翻译：用于互连结构的贵金属盖
公开(公告)号：US08497580B2
公开(公告)日：2013-07-30
申请号：US13191090
申请日：2011-07-26
申请人： Chih-Chao Yang , Daniel C. Edelstein , Fenton R. McFeely
发明人： Chih-Chao Yang , Daniel C. Edelstein , Fenton R. McFeely
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76826 , H01L21/76849 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.
摘要翻译：提供了包括具有约3.0或更小介电常数的介电材料的互连结构。该低k电介质材料具有至少一个具有嵌入其中的上表面的导电材料。电介质材料还具有在形成贵金属盖之前被制成疏水性的表面层。贵金属盖直接位于至少一个导电材料的上表面上。由于在电介质材料上存在疏水表面层，贵金属盖基本上不会延伸到与至少一种导电材料相邻的电介质材料的疏水表面层上，并且没有贵金属帽的金属残留物沉积形式在该疏水电介质表面上。

6. 发明申请

US20120326311A1 ENHANCED DIFFUSION BARRIER FOR INTERCONNECT STRUCTURES 有权
标题翻译：用于互连结构的增强扩展障碍
公开(公告)号：US20120326311A1
公开(公告)日：2012-12-27
申请号：US13164929
申请日：2011-06-21
申请人： Chih-Chao Yang , Daniel C. Edelstein , Steven E. Molis
发明人： Chih-Chao Yang , Daniel C. Edelstein , Steven E. Molis
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/52 , H01L21/3105 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L21/76846 , H01L21/76867 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, the method includes forming at least one opening into an interconnect dielectric material. A nitrogen enriched dielectric surface layer is formed within exposed surfaces of the interconnect dielectric material utilizing thermal nitridation. A metal diffusion barrier liner is formed on the nitrogen enriched dielectric surface. During and/or after the formation of the metal diffusion barrier liner, a metal nitride liner forms in-situ in a lower region of the metal diffusion barrier liner. A conductive material is then formed on the metal diffusion barrier liner. The conductive material, the metal diffusion barrier liner and the metal nitride liner that are located outside of the at least one opening are removed to provide a planarized conductive material, a planarized metal diffusion barrier liner and a planarized metal nitride liner, each of which includes an upper surface that is co-planar with the nitrogen enriched dielectric surface layer of the interconnect dielectric material.
摘要翻译：提供制造互连结构的替代方法，其中提供包括在互连电介质材料和上覆金属扩散阻挡衬里之间形成的原位形成的金属氮化物衬垫的增强扩散屏障。在一个实施例中，该方法包括在互连电介质材料中形成至少一个开口。利用热氮化在互连电介质的暴露表面内形成富氮介电表面层。在富氮电介质表面上形成金属扩散阻挡衬垫。在形成金属扩散阻挡衬里期间和/或之后，金属氮化物衬垫在金属扩散阻挡衬里的下部区域中原位形成。然后在金属扩散阻挡衬里上形成导电材料。移除位于至少一个开口外侧的导电材料，金属扩散阻挡衬垫和金属氮化物衬垫，以提供平坦化的导电材料，平坦化的金属扩散阻挡衬垫和平坦化的金属氮化物衬垫，每个衬垫包括与互连电介质材料的富氮介电表面层共平面的上表面。

7. 发明授权

US08232645B2 Interconnect structures, design structure and method of manufacture 有权
标题翻译：互连结构，设计结构和制造方法
公开(公告)号：US08232645B2
公开(公告)日：2012-07-31
申请号：US12191522
申请日：2008-08-14
申请人： Chih-Chao Yang , Kaushik Chanda , Daniel C. Edelstein
发明人： Chih-Chao Yang , Kaushik Chanda , Daniel C. Edelstein
IPC分类号： H01L23/48
CPC分类号： H01L23/5329 , H01L21/76846 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is provided that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing. The metal interconnect is formed in a dielectric material. A metal cap is selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.
摘要翻译：提供了一种互连结构，其基本上消除了电迁移（EM）损伤，设计结构和制造方法。金属互连形成在电介质材料中。金属盖对金属互连有选择性。金属盖包括RuX，其中X在硼，磷或硼和磷的组合。

8. 发明授权

US07964966B2 Via gouged interconnect structure and method of fabricating same 有权
标题翻译：通过沟槽互连结构及其制造方法
公开(公告)号：US07964966B2
公开(公告)日：2011-06-21
申请号：US12494564
申请日：2009-06-30
申请人： Chih-Chao Yang , Daniel C. Edelstein , Theodorus E. Standaert
发明人： Chih-Chao Yang , Daniel C. Edelstein , Theodorus E. Standaert
IPC分类号： H01L23/48 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76808 , H01L21/76805 , H01L21/76844 , H01L21/76846 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure including a gouging feature at the bottom of a via opening and a method of forming the same are provided. The method of the present invention does not disrupt the coverage of the deposited trench diffusion barrier in a line opening that is located atop the via opening, and/or does not introduce damages caused by creating a gouging feature at the bottom of the via opening by sputtering into the interconnect dielectric material that includes the via and line openings. Such an interconnect structure is achieved by providing a gouging feature in the bottom of the via opening by first forming the line opening within the interconnect dielectric, followed by forming the via opening and then the gouging feature.
摘要翻译：提供一种包括通孔开口底部的气刨结构的互连结构及其形成方法。本发明的方法不会破坏位于通孔开口顶部的线路开口中的沉积的沟槽扩散阻挡层的覆盖和/或不引起由于在通孔开口的底部产生气流特征而造成的损害溅射到包括通孔和线路开口的互连电介质材料中。通过首先在互连电介质中形成线路开口，然后形成通孔开口，然后形成沟槽特征，在通孔开口的底部提供气泡特征来实现这种互连结构。

9. 发明授权

US07956463B2 Large grain size conductive structure for narrow interconnect openings 有权
标题翻译：用于窄互连开口的大粒度导电结构
公开(公告)号：US07956463B2
公开(公告)日：2011-06-07
申请号：US12560878
申请日：2009-09-16
申请人： Chih-Chao Yang , Daniel C. Edelstein , Takeshi Nogami , Stephen M. Rossnagel
发明人： Chih-Chao Yang , Daniel C. Edelstein , Takeshi Nogami , Stephen M. Rossnagel
IPC分类号： H01L23/48
CPC分类号： H01L21/76871 , H01L21/76846 , H01L21/76868 , H01L21/76883
摘要： An interconnect structure having reduced electrical resistance and a method of forming such an interconnect structure are provided. The interconnect structure includes a dielectric material including at least one opening therein. The at least one opening is filled with an optional barrier diffusion layer, a grain growth promotion layer, an agglomerated plating seed layer, an optional second plating seed layer a conductive structure. The conductive structure which includes a metal-containing conductive material, typically Cu, has a bamboo microstructure and an average grain size of larger than 0.05 microns. In some embodiments, the conductive structure includes conductive grains that have a (111) crystal orientation.
摘要翻译：提供具有降低的电阻的互连结构和形成这种互连结构的方法。互连结构包括其中包括至少一个开口的电介质材料。至少一个开口填充有可选的阻挡扩散层，晶粒生长促进层，聚集的电镀种子层，任选的第二电镀种子层，导电结构。包含含金属的导电材料（通常为Cu）的导电结构具有竹结构，平均晶粒尺寸大于0.05微米。在一些实施例中，导电结构包括具有（111）晶体取向的导电晶粒。

10. 发明申请

US20110062587A1 LARGE GRAIN SIZE CONDUCTIVE STRUCTURE FOR NARROW INTERCONNECT OPENINGS 有权
标题翻译：用于窄幅互连开口的大粒度导电结构
公开(公告)号：US20110062587A1
公开(公告)日：2011-03-17
申请号：US12560878
申请日：2009-09-16
申请人： Chih-Chao Yang , Daniel C. Edelstein , Takeshi Nogami , Stephen M. Rossnagel
发明人： Chih-Chao Yang , Daniel C. Edelstein , Takeshi Nogami , Stephen M. Rossnagel
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76871 , H01L21/76846 , H01L21/76868 , H01L21/76883
摘要： An interconnect structure having reduced electrical resistance and a method of forming such an interconnect structure are provided. The interconnect structure includes a dielectric material including at least one opening therein. The at least one opening is filled with an optional barrier diffusion layer, a grain growth promotion layer, an agglomerated plating seed layer, an optional second plating seed layer a conductive structure. The conductive structure which includes a metal-containing conductive material, typically Cu, has a bamboo microstructure and an average grain size of larger than 0.05 microns. In some embodiments, the conductive structure includes conductive grains that have a (111) crystal orientation.
摘要翻译：提供具有降低的电阻的互连结构和形成这种互连结构的方法。互连结构包括其中包括至少一个开口的电介质材料。至少一个开口填充有可选的阻挡扩散层，晶粒生长促进层，聚集的电镀种子层，任选的第二电镀种子层，导电结构。包含含金属的导电材料（通常为Cu）的导电结构具有竹结构，平均晶粒尺寸大于0.05微米。在一些实施例中，导电结构包括具有（111）晶体取向的导电晶粒。

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