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    • 4. 发明授权
    • Multiple layer resist scheme implementing etch recipe particular to each layer
    • 多层抗蚀剂方案实现每层特有的蚀刻配方
    • US07352064B2
    • 2008-04-01
    • US10904323
    • 2004-11-04
    • Nicholas C. M. FullerTimothy J. DaltonRaymond JoyYi-hsiung LinChun Hui Low
    • Nicholas C. M. FullerTimothy J. DaltonRaymond JoyYi-hsiung LinChun Hui Low
    • H01L23/48H01L23/52H01L29/40H01L21/4763
    • H01L21/76802H01L21/0332H01L21/31138H01L21/31144
    • Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.
    • 公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸(CD)的方法和实现的抗蚀剂方案。 该方法包括形成多层抗蚀剂方案,该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层,平坦化层上的第二类型材料的第二电介质层,以及在电介质上的第三类型材料的第三光致抗蚀剂层 层。 有机材料和无机材料之间的材料类型是交替的。 第三层被图案化为金属线和/或经由CD。 然后使用对每一个被暴露的第一光致抗蚀剂层,第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。 提供准确的CD形成和足够的抗蚀剂预算。
    • 9. 发明授权
    • Resist stripping methods using backfilling material layer
    • 使用回填材料层的抗剥落方法
    • US07935637B2
    • 2011-05-03
    • US11839934
    • 2007-08-16
    • Nicholas C. M. FullerSivananda KanakasabapathyYing Zhang
    • Nicholas C. M. FullerSivananda KanakasabapathyYing Zhang
    • H01L21/302H01L21/461
    • H01L21/31133H01L21/31058H01L21/31138
    • A method for fabricating a microelectronic structure provides for forming a backfilling material layer at least laterally adjacent, and preferably laterally adjoining, a resist layer located over a substrate. Preferably, the resist layer comprises a surface treated resist layer. Optionally, the backfilling material layer may be surface treated similarly to the surface treated resist layer. Under such circumstances: (1) surface portions of the backfilling material layer and resist layer; and (2) remaining portions of the backfilling material layer and resist layer, may be sequentially stripped using a two step etch method, such as a two step plasma etch method. Alternatively, a surface portion of the surface treated resist layer only may be stripped while using a first etch method, and the remaining portions of the resist layer and backfilling material layer may be planarized prior to being simultaneously stripped while using a second etch method.
    • 用于制造微电子结构的方法提供了形成位于衬底上方的至少侧向邻近且优选地横向邻接的抗蚀剂层的回填材料层。 优选地,抗蚀剂层包括表面处理的抗蚀剂层。 任选地,回填材料层可以与表面处理的抗蚀剂层类似地进行表面处理。 在这种情况下:(1)回填材料层和抗蚀剂层的表面部分; 和(2)回填材料层和抗蚀剂层的剩余部分可以使用两步蚀刻方法,例如两步等离子体蚀刻方法来顺序剥离。 或者,仅使用第一蚀刻方法剥离表面处理的抗蚀剂层的表面部分,并且可以在使用第二蚀刻方法同时剥离之前将抗蚀剂层和回填材料层的其余部分平坦化。