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31. 发明授权

US06893910B1 One step deposition method for high-k dielectric and metal gate electrode 有权
标题翻译：一种用于高k电介质和金属栅电极的沉积方法
公开(公告)号：US06893910B1
公开(公告)日：2005-05-17
申请号：US10462670
申请日：2003-06-17
申请人： Christy Mei-Chu Woo , Paul R. Besser , Minh Van Ngo , James N. Pan , Jinsong Yin
发明人： Christy Mei-Chu Woo , Paul R. Besser , Minh Van Ngo , James N. Pan , Jinsong Yin
IPC分类号： H01L21/28 , H01L21/316 , H01L21/336 , H01L29/49 , H01L29/51 , H01L29/78 , H01L21/338 , H01L21/31 , H01L21/3205
CPC分类号： H01L21/28185 , H01L21/28079 , H01L21/28194 , H01L21/31683 , H01L29/4958 , H01L29/511 , H01L29/517 , H01L29/66545 , H01L29/66583 , H01L29/7833
摘要： A method for forming a semiconductor structure removes the temporary gate formed on the dielectric layer to expose a recess in which oxygen-rich CVD oxide is deposited. A tantalum layer is then deposited by low-power physical vapor deposition on the CVD oxide. Annealing is then performed to create a Ta2O5 region and a Ta region from the deposited oxide and Ta. This creates a low carbon-content Ta2O5 and a metallic Ta gate in a single process step.
摘要翻译：用于形成半导体结构的方法去除形成在电介质层上的临时栅极以暴露其中沉积有富氧CVD氧化物的凹槽。然后通过低功率物理气相沉积在CVD氧化物上沉积钽层。然后进行退火以从沉积的氧化物和Ta形成Ta 2 O 5区域和Ta区域。这在单一工艺步骤中产生低碳含量的Ta 2 O 5 O 5和金属Ta浇口。

32. 发明授权

US06727560B1 Engineered metal gate electrode 有权
公开(公告)号：US06727560B1
公开(公告)日：2004-04-27
申请号：US10360719
申请日：2003-02-10
申请人： James N. Pan , Paul R. Besser , Christy Woo , Minh Van Ngo , Jinsong Yin
发明人： James N. Pan , Paul R. Besser , Christy Woo , Minh Van Ngo , Jinsong Yin
IPC分类号： H01L2976
CPC分类号： H01L29/66545 , H01L21/28088 , H01L29/4966
摘要： A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

33. 发明授权

US06387767B1 Nitrogen-rich silicon nitride sidewall spacer deposition 失效
标题翻译：富氮氮化硅侧壁间隔物沉积
公开(公告)号：US06387767B1
公开(公告)日：2002-05-14
申请号：US09781448
申请日：2001-02-13
申请人： Paul R. Besser , Minh Van Ngo , Christy Mei-Chu Woo , George Jonathan Kluth
发明人： Paul R. Besser , Minh Van Ngo , Christy Mei-Chu Woo , George Jonathan Kluth
IPC分类号： H01L21336
CPC分类号： H01L29/665
摘要： Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and source/drain regions using salicide technology without associated bridging between the metal silicide layer on the gate electrode and the metal silicide layers over the source/drain regions. Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming nitrogen-rich silicon nitride sidewall spacers with increased nitrogen, thereby eliminating free Si available to react with the metal subsequently deposited and thus avoiding the formation of metal silicide on the sidewall spacers.
摘要翻译：使用富含氮的氮化硅侧壁间隔物实现自杀处理，其允许使用硅化物技术在多晶硅栅极电极和源极/漏极区域上形成金属硅化物层，例如NiSi，而不会在栅极上的金属硅化物层之间相互桥接和源极/漏极区域之间的金属硅化物层。通过形成具有增加的富氮氮化硅侧壁间隔物，避免了金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的结合氮，从而消除可用于随后沉积的金属的游离Si，从而避免在侧壁间隔物上形成金属硅化物。

34. 发明授权

US06329718B1 Method for reducing stress-induced voids for 0.25m&mgr; and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby 失效
标题翻译：通过退火互连线和使用低偏压和低层间电介质沉积速率减少应力诱发的0.25μm及更小的半导体芯片技术的空穴的方法，由此制成半导体芯片
公开(公告)号：US06329718B1
公开(公告)日：2001-12-11
申请号：US09105775
申请日：1998-06-26
申请人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick MacCrae , Richard J. Huang , Khanh Tran
发明人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick MacCrae , Richard J. Huang , Khanh Tran
IPC分类号： H01L2348
CPC分类号： H01L21/7685 , H01L21/76837 , H01L21/76858 , H01L21/76885 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.
摘要翻译：用于制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。在退火期间，形成铝和钛的合金，其随后容积收缩，收缩被铝吸收。因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。因此，互连线中不希望的空隙形成的可能性降低。在随后的ILD间隙填充沉积过程中，通过使用相对低的偏置功率来降低气相沉积温度，并且通过使用相对较低的源气体沉积流速来减少互连线上的流动引起的压缩应力，仍然进一步降低了不希望的空隙形成的可能性在ILD形成期间。

35. 发明授权

US06228761B1 Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide 有权
标题翻译：形成具有改善的二氧化硅/硅化物蚀刻选择性的局部互连的方法
公开(公告)号：US06228761B1
公开(公告)日：2001-05-08
申请号：US09417840
申请日：1999-10-14
申请人： Minh Van Ngo , Paul R. Besser
发明人： Minh Van Ngo , Paul R. Besser
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/3144 , H01L21/3145 , H01L21/3185 , H01L21/76895
摘要： A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge introduces additional nitrogen from a nitrogen plasma into a nitrogen-containing etch stop layer (e.g., SiON) that has already been deposited by plasma enhanced chemical vapor deposition (PECVD), for example. The enriched nitrogen etch stop layer is harder to etch than conventional PECVD SiON so that when etching the dielectric layer in which the local interconnect material is to be subsequently deposited, the etching stops at the etch stop layer in a controlled manner. This prevents the unintentional etching of the silicide region and diffusion region at the field edge.
摘要翻译：用于形成局部互连而不削弱场边缘或在场边缘处断开扩散区的方法和装置将来自氮等离子体的附加氮引入已经通过等离子体沉积的含氮蚀刻停止层（例如，SiON）增强化学气相沉积（PECVD）。富集的氮蚀刻停止层比常规PECVD SiON难以蚀刻，使得当蚀刻其中将要沉积局部互连材料的电介质层时，蚀刻以受控的方式在蚀刻停止层处停止。这防止了在场边缘处的硅化物区域和扩散区域的无意蚀刻。

36. 发明授权

US06204136B1 Post-spacer etch surface treatment for improved silicide formation 有权
标题翻译：间隔后蚀刻表面处理以改善硅化物形成
公开(公告)号：US06204136B1
公开(公告)日：2001-03-20
申请号：US09386466
申请日：1999-08-31
申请人： Simon S. Chan , Minh Van Ngo , Paul R. Besser , Angela T. Hui
发明人： Simon S. Chan , Minh Van Ngo , Paul R. Besser , Angela T. Hui
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/31116
摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.
摘要翻译：通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣。实施方案包括通过进行氢离子等离子体处理来除去碳质残渣。

37. 发明授权

US06174743B1 Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines 失效
标题翻译：降低半导体互连线中应力诱发空隙的发生率的方法
公开(公告)号：US06174743B1
公开(公告)日：2001-01-16
申请号：US09208623
申请日：1998-12-08
申请人： Suzette K. Pangrle , Paul R. Besser , Minh Van Ngo
发明人： Suzette K. Pangrle , Paul R. Besser , Minh Van Ngo
IPC分类号： H01L2131
CPC分类号： H01L21/3145 , H01L21/31612 , H01L21/76801
摘要： In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, a SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. During deposition, silane flow rates are regulating and reducing to less than sixty standard cubic centimeters per minute, thereby reducing the incidence of stress-induced voiding in the underlying interconnect lines. During deposition adjustments are made in deposition temperature and process pressure to control the characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO2 layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing.
摘要翻译：在基板的微电路互连线上形成层间电介质（ILD）涂层的方法中，通过使用等离子体增强化学气相沉积形成SiON层。使用由氮气，一氧化二氮和硅烷气体形成的等离子体的沉积，其中气体以稳定的流速分配并由射频电源激励。等离子体反应形成沉积在半导体衬底上的SiON。在沉积期间，硅烷流速调节并降低到每分钟少于六十标准立方厘米，从而降低底层互连线中应力引起的空隙的发生。在淀积温度和工艺压力下进行沉积调整，以控制SiON层的特性。测试SiON层的可接受的光学性能，并且用SiO 2层涂覆可接受的SiON层以完成ILD的形成。一旦形成了ILD，底物就可以进行进一步的处理。

38. 发明授权

US6150285A Method for simultaneous deposition and sputtering of TEOS 失效
标题翻译：同时沉积和溅射TEOS的方法
公开(公告)号：US6150285A
公开(公告)日：2000-11-21
申请号：US99057
申请日：1998-06-17
申请人： Paul R. Besser , Minh Van Ngo
发明人： Paul R. Besser , Minh Van Ngo
IPC分类号： H01L21/316 , H01L21/768 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/31612 , H01L21/76801
摘要： A method for making 0.25 micron semiconductor chips includes using TEOS as the high density plasma (HDP) inter-layer dielectric (ILD). More specifically, after establishing a predetermined aluminum line pattern on a substrate, TEOS is deposited and simultaneously with the TEOS deposition, excess TEOS is etched away, thereby avoiding hydrogen embrittlement of and subsequent void formation in the aluminum lines that could otherwise occur if silane were used as the HDP ILD.
摘要翻译：制造0.25微米半导体芯片的方法包括使用TEOS作为高密度等离子体（HDP）层间电介质（ILD）。更具体地说，在基板上建立预定的铝线图案之后，TEOS沉积并与TEOS沉积同时被蚀刻掉，从而避免了铝线中的氢脆化和随后的空隙形成，否则如果硅烷是用作HDP ILD。

39. 发明授权

US06576548B1 Method of manufacturing a semiconductor device with reliable contacts/vias 有权
标题翻译：制造具有可靠接触/通孔的半导体器件的方法
公开(公告)号：US06576548B1
公开(公告)日：2003-06-10
申请号：US10079861
申请日：2002-02-22
申请人： Amy Tu , Minh Van Ngo , Austin Frenkel , Robert J. Chiu , Jeff Erhardt
发明人： Amy Tu , Minh Van Ngo , Austin Frenkel , Robert J. Chiu , Jeff Erhardt
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/31105 , H01L21/76804 , H01L21/76846 , H01L21/76877
摘要： Reliable contacts/vias are formed by sputter etching to flare exposed edges of an opening formed in a dielectric layer, depositing a composite barrier layer and then filling the opening with tungsten at a low deposition rate. The resulting contact/via exhibits significantly reduced porosity and contact resistance. Embodiments include sputter etching to incline the edges of an opening formed in an oxide dielectric layer, e.g., a silicon oxide derived from TEOS or BPSG, at an angle of about 83° to about 86°, depositing a thin layer of Ti, e.g., at a thickness of about 250 Å to about 350 Å, depositing at least one layer of titanium nitride, e.g., three layers of titanium nitride, at a total thickness of about 130 Å to about 170 Å, and then depositing tungsten at a deposition rate of about 1,900 to about 2,300 Å/min to fill the opening.
摘要翻译：通过溅射蚀刻形成可靠的触点/通孔，以对形成在电介质层中的开口的暴露边缘进行曝光，沉积复合阻挡层，然后以低沉积速率用钨填充开口。所得到的接触/通孔显示出显着降低的孔隙率和接触电阻。实施例包括溅射蚀刻，以约83°至约86°的角度倾斜形成在氧化物电介质层中的开口的边缘，例如衍生自TEOS或BPSG的氧化硅，沉积Ti薄层，在约250埃至大约350埃的厚度上沉积至少一层氮化钛，例如三层氮化钛，总厚度为约至约为170埃，然后以沉积速率沉积钨约1,900至约2,300埃/分钟以填充开口。

40. 发明申请

US20090050471A1 PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING LAYERS WITHIN OPENINGS 审中-公开
标题翻译：形成电子器件的方法，包括开孔中的沉积层
公开(公告)号：US20090050471A1
公开(公告)日：2009-02-26
申请号：US11844518
申请日：2007-08-24
申请人： Robert J. Chiu , Connie Pin-Chin Wang , Minh Van Ngo , Simon S. Chan
发明人： Robert J. Chiu , Connie Pin-Chin Wang , Minh Van Ngo , Simon S. Chan
IPC分类号： C23C14/32
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76814 , H01L23/485
摘要： A process of forming an electronic device can include depositing a first layer over a substrate and depositing a second layer over the first layer. In one embodiment, depositing the first layer is performed at a first alternating current (“AC”) power, and depositing the second layer is performed at a second AC power that is different from the first AC power. In another embodiment, the first layer is formed by a physical vapor deposition technique at a first power sufficient to remove the insulating layer using first metal ions, wherein the first layer includes an overhanging portion extending over the bottom of the opening. In a further embodiment, the second layer is formed by the physical vapor deposition technique using second metal ions and a second power sufficient to reduce a lateral dimension of the overhanging portion.
摘要翻译：形成电子器件的过程可以包括在衬底上沉积第一层并在第一层上沉积第二层。在一个实施例中，在第一交流（“AC”）功率下执行沉积第一层，并且以不同于第一AC电力的第二AC电源执行沉积第二层。在另一个实施例中，第一层通过物理气相沉积技术以足以使用第一金属离子去除绝缘层的第一功率形成，其中第一层包括在开口底部延伸的伸出部分。在另一个实施例中，第二层通过使用第二金属离子的物理气相沉积技术和足以减少突出部分的横向尺寸的第二功率形成。

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