专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06576548B1 Method of manufacturing a semiconductor device with reliable contacts/vias 有权
标题翻译：制造具有可靠接触/通孔的半导体器件的方法
公开(公告)号：US06576548B1
公开(公告)日：2003-06-10
申请号：US10079861
申请日：2002-02-22
申请人： Amy Tu , Minh Van Ngo , Austin Frenkel , Robert J. Chiu , Jeff Erhardt
发明人： Amy Tu , Minh Van Ngo , Austin Frenkel , Robert J. Chiu , Jeff Erhardt
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/31105 , H01L21/76804 , H01L21/76846 , H01L21/76877
摘要： Reliable contacts/vias are formed by sputter etching to flare exposed edges of an opening formed in a dielectric layer, depositing a composite barrier layer and then filling the opening with tungsten at a low deposition rate. The resulting contact/via exhibits significantly reduced porosity and contact resistance. Embodiments include sputter etching to incline the edges of an opening formed in an oxide dielectric layer, e.g., a silicon oxide derived from TEOS or BPSG, at an angle of about 83° to about 86°, depositing a thin layer of Ti, e.g., at a thickness of about 250 Å to about 350 Å, depositing at least one layer of titanium nitride, e.g., three layers of titanium nitride, at a total thickness of about 130 Å to about 170 Å, and then depositing tungsten at a deposition rate of about 1,900 to about 2,300 Å/min to fill the opening.
摘要翻译：通过溅射蚀刻形成可靠的触点/通孔，以对形成在电介质层中的开口的暴露边缘进行曝光，沉积复合阻挡层，然后以低沉积速率用钨填充开口。所得到的接触/通孔显示出显着降低的孔隙率和接触电阻。实施例包括溅射蚀刻，以约83°至约86°的角度倾斜形成在氧化物电介质层中的开口的边缘，例如衍生自TEOS或BPSG的氧化硅，沉积Ti薄层，在约250埃至大约350埃的厚度上沉积至少一层氮化钛，例如三层氮化钛，总厚度为约至约为170埃，然后以沉积速率沉积钨约1,900至约2,300埃/分钟以填充开口。

IPRDB

热门服务

关于我们

友情链接

联系方式