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31. 发明授权

US07375708B2 Image display panel, image display apparatus and image display method 有权
标题翻译：图像显示面板，图像显示装置和图像显示方法
公开(公告)号：US07375708B2
公开(公告)日：2008-05-20
申请号：US10105652
申请日：2002-03-25
申请人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Yasuhiro Yoshida , Hiroyuki Furukawa
发明人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Yasuhiro Yoshida , Hiroyuki Furukawa
IPC分类号： G09G3/36
CPC分类号： G09G3/2011 , G09G3/2051 , G09G3/3648 , G09G3/3688 , G09G2300/0408 , G09G2310/027 , G09G2310/0297
摘要： A data signal line drive circuit supplying a video signal to a pixel array performs pseudo tone gradation processing with respect to the video signal that is sent to an n number of data signal lines SL by m (
摘要翻译：向像素阵列提供视频信号的数据信号线驱动电路相对于通过伪色调灰度处理的m（

32. 发明授权

US07339570B2 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 有权
标题翻译：数据信号线驱动电路，驱动电路，并入其的图像显示装置，以及使用该数据信号线的电子装置
公开(公告)号：US07339570B2
公开(公告)日：2008-03-04
申请号：US09851885
申请日：2001-05-09
申请人： Yasushi Kubota , Hajime Washio , Michael James Brownlow , Graham Andrew Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael James Brownlow , Graham Andrew Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G3/36
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.
摘要翻译：图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。

33. 发明申请

US20070242021A1 Level shifter circuit and display device provided therewith 有权
公开(公告)号：US20070242021A1
公开(公告)日：2007-10-18
申请号：US11812461
申请日：2007-06-19
申请人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
发明人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
IPC分类号： H03K19/0175
CPC分类号： G09G3/3611 , G09G2300/0408 , G09G2310/0289 , H03K19/0013 , H03K19/018521
摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

34. 发明授权

US07202846B2 Signal line drive circuit and display device using the same 有权
标题翻译：信号线驱动电路及使用其的显示装置
公开(公告)号：US07202846B2
公开(公告)日：2007-04-10
申请号：US10440077
申请日：2003-05-15
申请人： Kazuhiro Maeda , Sachio Tsujino , Keiji Takahashi , Hajime Washio
发明人： Kazuhiro Maeda , Sachio Tsujino , Keiji Takahashi , Hajime Washio
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0294 , G09G2330/021 , G09G2340/0421
摘要： A data signal line drive circuit is provided with: a shift register belonging to a system, whose stages correspond to respective sampling units for driving odd-number-th data signal lines; and a shift register belonging to another system, whose stages correspond to respective sampling units for driving even-number-th data signal lines. On the occasion of low-resolution mode, only either of the shift registers is operated, and in accordance with the outputs from the respective stages of the shift register which has been operated, timing signals, which are supplied to the sampling units corresponding to the stages of both shift registers, are generated. With this arrangement, even if one of input signals each having different signal line resolution is inputted, a signal line drive circuit which consumes a small amount of electric power can be realized, while it is possible to specify the timings of the operation of signal line drive sections for driving signal lines, in accordance with the input signal.
摘要翻译：数据信号线驱动电路具有：属于系统的移位寄存器，其级对应于用于驱动奇数数据信号线的相应采样单元; 以及属于另一系统的移位寄存器，其级对应于用于驱动第二数据信号线的相应采样单元。在低分辨率模式的情况下，仅移动寄存器中的任一个被操作，并且根据已经被操作的移位寄存器的各个级的输出，定时信号被提供给对应于生成两个移位寄存器的阶段。通过这样的配置，即使输入信号线分辨率不同的输入信号之一，也可以实现消耗少量电力的信号线驱动电路，同时可以规定信号线的动作时序用于驱动信号线的驱动部分，根据输入信号。

35. 发明授权

US06996203B2 Bidirectional shift register and display device incorporating same 失效
标题翻译：双向移位寄存器和包含其的显示装置
公开(公告)号：US06996203B2
公开(公告)日：2006-02-07
申请号：US10860660
申请日：2004-06-04
申请人： Mamoru Onda , Hajime Washio , Shunsuke Hayashi , Hiroshi Murofushi , Nobuhiko Suzuki
发明人： Mamoru Onda , Hajime Washio , Shunsuke Hayashi , Hiroshi Murofushi , Nobuhiko Suzuki
IPC分类号： G11C19/00
CPC分类号： G06F5/01 , G09G3/006 , G09G3/20 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0289 , G09G2330/12
摘要： The present invention includes: a shift register section, including multiple-stage flip-flops operating in synchronism with a clock signal, for switching a shift direction in accordance with an externally supplied direction instruct signal; a waveform change section for changing in waveform a signal output of one of the flip-flops which is in a first predetermined stage; and an inspection signal switching section for switching, in accordance with the direction instruct signal, an output between the signal output which has been changed in waveform in the waveform change section and a signal output of one of the flip-flops which is in a second predetermined stage.
摘要翻译：本发明包括：移位寄存器部分，包括与时钟信号同步操作的多级触发器，用于根据外部提供的方向指示信号切换移位方向; 波形变化部分，用于改变处于第一预定阶段的触发器之一的信号输出的波形; 以及检查信号切换部，根据方向指示信号，切换波形变化部中波形变化的信号输出与第二个触发器中的一个触发器的信号输出之间的输出预定阶段。

36. 发明申请

US20050243588A1 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 有权
标题翻译：数据信号线驱动电路，驱动电路，并入其的图像显示装置，以及使用该数据信号线的电子装置
公开(公告)号：US20050243588A1
公开(公告)日：2005-11-03
申请号：US11091012
申请日：2005-03-25
申请人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G3/20 , G09G3/36 , G09G5/00 , H01L21/77 , H01L21/84 , G11C5/06
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.
摘要翻译：图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。

37. 发明申请

US20050175138A1 Shift register and display device 有权
标题翻译：移位寄存器和显示设备
公开(公告)号：US20050175138A1
公开(公告)日：2005-08-11
申请号：US11044003
申请日：2005-01-28
申请人： Eiji Matsuda , Yuhichiroh Murakami , Sachio Tsujino , Hajime Washio
发明人： Eiji Matsuda , Yuhichiroh Murakami , Sachio Tsujino , Hajime Washio
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G11C19/00 , G11C19/28 , H03K17/693
CPC分类号： G09G3/3688 , G11C19/00 , G11C19/28
摘要： In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage. According to the above arrangement, it is possible to realize a shift register which does not malfunction and functions properly even in cases where two clock signals SCK and SCKB inputted to the shift register and having different phases from each other are out of phase. It is also possible to realize a display device having the shift register.
摘要翻译：在本发明的移位寄存器中，每个触发器具有作为故障防止电路的相位差检测部分和波形定时形成部分。相位差检测部分检测由时钟信号SCK和SCKB之间的相位差引起的重叠波形，并且生成从其重叠部分被去除的输出信号A（A 1，A 2，...）。波形定时形成部输出通过提取在对应的相位差检测部中产生的输出信号A（A 1，A 2，...）的周期而获得的输出信号X（X 1，X 2，...）当来自相应触发器的输出信号Q（Q 1，Q 2，...）为高时，为高电平。输出信号X（X 1，X 2，...）在下一阶段设置触发器。根据上述结构，即使在输入到移位寄存器的两个时钟信号SCK，SCKB彼此相位不同的情况下也可以实现不发生故障的功能，也能正常工作的移位寄存器。也可以实现具有移位寄存器的显示装置。

38. 发明授权

US06909417B2 Shift register and image display apparatus using the same 有权
标题翻译：移位寄存器和使用其的图像显示装置
公开(公告)号：US06909417B2
公开(公告)日：2005-06-21
申请号：US09578440
申请日：2000-05-25
申请人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
发明人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G11C19/00 , G09G3/20 , G09G3/36
CPC分类号： G09G3/3688 , G09G2300/0408 , G09G2310/0289 , G09G2330/021
摘要： A level shifter 13 is provided for each of SR flip flops F1 constituting a shift register 11. The level shifter 13 increases a voltage of a clock signal CK. This arrangement reduces a distance for transmitting a clock signal whose voltage has been increased, as compared with a construction in which a voltage of a clock signal is increased by a single level shifter and the signal is transmitted to each of the flip flops; consequently, a load capacity of the level shifter can be smaller. Furthermore, each of the level shifters is operated during a pulse output of the previous level shifter 13, and the operation is suspended at the end of the pulse output. Thus, the level shifters 13 can operate only when it is necessary to apply a clock signal CK to the corresponding SR flip flop F1. As a result, even when an amplitude of a clock signal is small, it is possible to reduce power consumption of the shift resister under normal operation.
摘要翻译：为构成移位寄存器11的每个SR触发器F 1提供电平移位器13.电平移位器13增加时钟信号CK的电压。与通过单个电平移位器增加时钟信号的电压并且将信号发送到每个触发器的结构相比，这种布置减少了用于传输电压已经增加的时钟信号的距离; 因此，电平转换器的负载能力可以更小。此外，每个电平移位器在先前电平移位器13的脉冲输出期间操作，并且在脉冲输出结束时暂停操作。因此，只有当需要对相应的SR触发器F 1施加时钟信号CK时，电平移位器13才能够工作。结果，即使当时钟信号的幅度小时，也可以降低功耗的正常运行中的移位寄存器。

39. 发明授权

US06879313B1 Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 有权
标题翻译：移位寄存器电路，具有电路的图像显示装置以及LCD装置的驱动方法
公开(公告)号：US06879313B1
公开(公告)日：2005-04-12
申请号：US09523511
申请日：2000-03-10
申请人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
发明人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
IPC分类号： G09G3/36 , G11C19/28 , G11C19/00
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.
摘要翻译：移位寄存器电路包括串联连接的多个锁存电路，以顺序地将脉冲信号ST从一个传送到另一个，一个发送时钟信号CLK的时钟信号线以及执行时钟信号之间的电连接和断开的多个开关电路线和多个锁存电路。在接通移位寄存器时，至少一个开关电路将至少一个锁存电路与时钟信号线电断开。在电源接通之后的初始化期间，时钟信号CLK的频率比正常运行期间低，并且在正常运行期间逐渐增大。

40. 发明授权

US06853324B2 Digital-to-analog conversion circuit and image display apparatus using the same 有权
标题翻译：数模转换电路和使用其的图像显示装置
公开(公告)号：US06853324B2
公开(公告)日：2005-02-08
申请号：US09952183
申请日：2001-09-13
申请人： Kazuhiro Maeda , Yasushi Kubota , Hajime Washio
发明人： Kazuhiro Maeda , Yasushi Kubota , Hajime Washio
IPC分类号： G02F1/136 , G02F1/133 , G02F1/1368 , G09G3/20 , G09G3/36 , H03M1/74 , H03M1/80 , H03M1/66
CPC分类号： H03M1/804 , G09G3/3688 , G09G2310/027
摘要： A digital-to-analog conversion circuit of charge distribution type includes a plurality of capacitors having respective capacitances that increase in a sequential order, one end of the capacitors being commonly connected electrically. The circuit also includes a plurality of analog switches each for electrically connecting a reference potential corresponding to a digital signal inputted from outside to the other end of the corresponding capacitor. These analog switches have respective driving capacities that increase in a sequential order.
摘要翻译：电荷分配型的数模转换电路包括多个电容器，其具有各自依次增加的电容，电容器的一端电连接。电路还包括多个模拟开关，每个模拟开关用于将与从外部输入的数字信号相对应的参考电位电连接到对应的电容器的另一端。这些模拟开关具有按照顺序增加的各自的驱动能力。

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