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31. 发明授权

US5640547A Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效
标题翻译：数据处理系统从输入时钟产生时钟信号，锁相到输入时钟并用于时钟逻辑器件
公开(公告)号：US5640547A
公开(公告)日：1997-06-17
申请号：US279887
申请日：1994-07-26
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/10 , H03K5/156 , H03L7/18 , G06F1/04
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
摘要翻译：一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时至少一对逻辑器件由时钟信号K1同步控制。

32. 发明授权

US5388249A Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效
公开(公告)号：US5388249A
公开(公告)日：1995-02-07
申请号：US872174
申请日：1992-04-22
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/10 , H03K5/156 , H03L7/18 , G06F1/12
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

33. 发明授权

US5345421A High speed, low noise semiconductor storage device 失效
标题翻译：高速，低噪音的半导体存储设备
公开(公告)号：US5345421A
公开(公告)日：1994-09-06
申请号：US905745
申请日：1992-06-29
申请人： Masahiro Iwamura , Tatsumi Yamauchi , Makoto Saeki , Hideaki Uchida
发明人： Masahiro Iwamura , Tatsumi Yamauchi , Makoto Saeki , Hideaki Uchida
IPC分类号： G11C11/417 , G11C11/401 , G11C11/409 , H03K19/003 , H03K19/00
CPC分类号： H03K19/00361
摘要： A wide-bit output semiconductor storage device of high speed and low noise is provided in which output circuits are grouped into two groups and the two output circuit groups are so controlled as to be switched in directions of levels which are opposite to each other.
摘要翻译：提供了一种高速和低噪声的宽位输出半导体存储器件，其中输出电路被分组成两组，并且两个输出电路组被如此控制以在彼此相反的电平的方向上切换。

34. 发明授权

US5239212A Gate circuit of combined field-effect and bipolar transistors with an improved discharge arrangement 失效
标题翻译：具有改善放电布置的组合场效应和双极晶体管的栅极电路
公开(公告)号：US5239212A
公开(公告)日：1993-08-24
申请号：US986891
申请日：1992-12-08
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H01L27/06 , H03K19/01 , H03K19/017 , H03K19/0944
CPC分类号： H03K19/01 , H01L27/0623 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.
摘要翻译：低功耗门电路结构包括互补场效应晶体管和双极型晶体管的组合，以及放电装置，用于在场效应晶体管和双极晶体管截止时从这些晶体管放电累积的电荷。

35. 发明授权

US4829201A Gate circuit of combined field-effect and bipolar transistors 失效
标题翻译：组合场效应和双极晶体管的门电路
公开(公告)号：US4829201A
公开(公告)日：1989-05-09
申请号：US127183
申请日：1987-12-01
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

36. 发明授权

US4813020A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4813020A
公开(公告)日：1989-03-14
申请号：US170623
申请日：1988-03-17
申请人： Masahiro Iwamura , Ikuro Masuda
发明人： Masahiro Iwamura , Ikuro Masuda
IPC分类号： H01L27/088 , G11C7/10 , G11C8/08 , G11C11/418 , G11C19/28 , H01L21/8234 , H01L21/8236 , H01L21/8249 , H01L27/06 , H03K17/687 , H03K19/013 , H03K19/08 , H03K19/082 , H03K19/0944 , G11C7/00
CPC分类号： G11C7/1057 , G11C11/418 , G11C19/28 , G11C7/1006 , G11C7/1051 , G11C8/08 , H03K19/0136 , H03K19/0826 , H03K19/09448 , G11C2207/108
摘要： A composite circuit including a MOS transistor and a bipolar transistor to be driven by the MOS transistors and forming an output stage, a logical inverter circuit connected to an output terminal of the composite circuit to invert the level of the output signal, and a MOS transistor having a source and a drain thereof parallelly connected across a collector and an emitter of the bipolar transistor are provided. When the bipolar transistor conducts with a voltage drop associated with a base-emitter voltage, the parallelly connected MOS transistor renders the bipolar transistor completely conductive so that a level-shiftless output signal is produced.
摘要翻译：一种复合电路，包括由MOS晶体管驱动并形成输出级的MOS晶体管和双极晶体管，连接到复合电路的输出端以反转输出信号电平的逻辑反相器电路和MOS晶体管具有并联连接在双极晶体管的集电极和发射极之间的源极和漏极。当双极晶体管以与基极 - 发射极电压相关联的电压降导通时，并联连接的MOS晶体管使双极晶体管完全导通，从而产生电平无移位输出信号。

37. 发明授权

US4694203A High speed bi-comos switching circuit 失效
标题翻译：高速双电源开关电路
公开(公告)号：US4694203A
公开(公告)日：1987-09-15
申请号：US716151
申请日：1985-03-26
申请人： Akira Uragami , Yukio Suzuki , Masahiro Iwamura , Ikuro Masuda
发明人： Akira Uragami , Yukio Suzuki , Masahiro Iwamura , Ikuro Masuda
IPC分类号： H03K19/08 , H03K17/04 , H03K17/0412 , H03K17/567 , H03K17/60 , H03K17/687 , H03K19/017 , H03K19/0944 , H03K19/013
CPC分类号： H03K17/04126 , H03K17/567 , H03K19/09448
摘要： A bipolar/CMOS mixed type switching circuit comprising two npn-type bipolar transistors Q.sub.1, Q.sub.2 that are connected in the form of a totem pole in the output stage, a CMOS inverter and an NMOSFET M.sub.3 for driving these transistors in a complementary manner, and resistance means R for discharging the electric charge stored in the base of the transistor Q.sub.2. The threshold voltage of an NMOSFET M.sub.2 constituting the CMOS inverter in the absence of substrate effect is set to be substantially equal to the threshold voltage of the NMOSFET M.sub.3 in the absence of the substrate effect, and the channel conductance W.sub.N /L.sub.N of the NMOSFET M.sub.3 is so set that the threshold voltage V.sub.LT1 of the CMOS inverter and the practical threshold voltage V.sub.LT2 of the NMOSFET M.sub.3 will be nearly the same. Owing to the above structure, there is obtained a switching circuit which permits little through current to flow and which operates at high speeds.
摘要翻译：一种双极/ CMOS混合型开关电路，包括在输出级以图腾柱形式连接的两个npn型双极晶体管Q1，Q2，CMOS反相器和用于以互补方式驱动这些晶体管的NMOSFET M3;以及用于对存储在晶体管Q2的基极中的电荷进行放电的电阻装置R. 在不存在衬底效应的情况下，构成CMOS反相器的NMOSFET M2的阈值电压被设置为在没有衬底效应的情况下基本上等于NMOSFET M3的阈值电压，并且NMOSFET M3的沟道电导WN / LN 被设置为使得CMOS反相器的阈值电压VLT1和NMOSFET M3的实际阈值电压VLT2将几乎相同。由于上述结构，所以获得了允许很少的直流电流并且高速运行的开关电路。

38. 发明授权

US4689503A Level conversion circuitry for a semiconductor integrated circuit utilizing bis CMOS circuit elements 失效
标题翻译：利用双CMOS电路元件的半导体集成电路的电平转换电路
公开(公告)号：US4689503A
公开(公告)日：1987-08-25
申请号：US575567
申请日：1984-01-31
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177 , H03K19/01 , H03K19/013 , H03K19/017
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

39. 发明申请

US20080211563A1 Interface Circuit, Power Conversion Device, and Vehicle-Mounted Electric Machinery System 审中-公开
标题翻译：接口电路，电源转换装置和车载电机系统
公开(公告)号：US20080211563A1
公开(公告)日：2008-09-04
申请号：US12026616
申请日：2008-02-06
申请人： Masamitsu Inaba , Masahiro Iwamura , Satoru Shigeta
发明人： Masamitsu Inaba , Masahiro Iwamura , Satoru Shigeta
IPC分类号： H03L5/00
CPC分类号： H03K19/018 , F02N2011/0888 , H03K19/00376
摘要： An interface circuit capable of reliably transmitting signal even when there is fluctuation in the potential difference in reference potentials between circuits between which signal transmission is carried out. An interface circuit 4 is comprised of a level shift circuit 20 and a potential selection circuit 10 for selecting the potential of a power supply voltage for operating the level shift circuit 20. The potential selection circuit 10 selects one of a plurality of input potentials. The level shift circuit 20 receives a voltage pulse having a first potential as reference potential and outputs a voltage pulse having a second potential as reference potential. The level shift circuit 20 is operated on the basis of both a potential difference between the output potential from the potential selection circuit and the first potential and a potential difference between the selected potential and the second potential.
摘要翻译：即使在执行信号传输的电路之间的参考电位的电位差发生波动时，也能够可靠地发送信号的接口电路。接口电路4包括电平移位电路20和用于选择用于操作电平移位电路20的电源电压的电位的电位选择电路10。电位选择电路10选择多个输入电位之一。电平移位电路20接收具有第一电位的电压脉冲作为参考电位，并输出具有第二电位的电压脉冲作为参考电位。电平移位电路20基于来自电势选择电路的输出电位与第一电位之间的电位差和所选择的电位与第二电位之间的电位差两者来操作。

40. 发明申请

US20060192534A1 Generating apparatus and motor control apparatus 有权
标题翻译：发电机和电机控制装置
公开(公告)号：US20060192534A1
公开(公告)日：2006-08-31
申请号：US11356075
申请日：2006-02-17
申请人： Tatsumi Yamauchi , Shinji Shirakawa , Masahiro Iwamura , Masamitsu Inaba , Keiichi Mashino , Keiji Kunii
发明人： Tatsumi Yamauchi , Shinji Shirakawa , Masahiro Iwamura , Masamitsu Inaba , Keiichi Mashino , Keiji Kunii
IPC分类号： H02H7/06 , H02P9/00 , H02P11/00
CPC分类号： H02P9/102 , H02P6/005 , H02P9/107 , H02P2101/45
摘要： A generator having a field coil L, and an SW1 control circuit 2 for controlling field current flowing through the field coil L. When a generating operation of the generator is to be ended, a switch 1 SW1 is turned off to interrupt the field current flowing through the field coil L, and a switch 2 SW2 is turned off to allow the field current remaining the field coil L to the current path including a resistance element 1 with a resistance element capable of quickly attenuating the field current.
摘要翻译：具有励磁线圈L的发电机和用于控制流过励磁线圈L的励磁电流的SW 1控制电路2.当发电机的发电操作结束时，开关1 SW 1断开以中断励磁流过励磁线圈L的电流和开关2 SW 2截止，使励磁线圈L的励磁电流保持在包括具有能够快速衰减励磁电流的电阻元件的电阻元件1的电流路径。

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