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1. 发明授权

US4890017A CMOS-BiCMOS gate circuit 失效
标题翻译： CMOS-BiCMOS门电路
公开(公告)号：US4890017A
公开(公告)日：1989-12-26
申请号：US127184
申请日：1987-12-01
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

2. 发明授权

US4719373A Gate circuit of combined field-effect and bipolar transistors 失效
标题翻译：组合场效应和双极晶体管的门电路
公开(公告)号：US4719373A
公开(公告)日：1988-01-12
申请号：US45216
申请日：1987-04-30
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952 , H03K17/60 , H03K3/33
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

3. 发明授权

US5239212A Gate circuit of combined field-effect and bipolar transistors with an improved discharge arrangement 失效
标题翻译：具有改善放电布置的组合场效应和双极晶体管的栅极电路
公开(公告)号：US5239212A
公开(公告)日：1993-08-24
申请号：US986891
申请日：1992-12-08
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H01L27/06 , H03K19/01 , H03K19/017 , H03K19/0944
CPC分类号： H03K19/01 , H01L27/0623 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.
摘要翻译：低功耗门电路结构包括互补场效应晶体管和双极型晶体管的组合，以及放电装置，用于在场效应晶体管和双极晶体管截止时从这些晶体管放电累积的电荷。

4. 发明授权

US4829201A Gate circuit of combined field-effect and bipolar transistors 失效
标题翻译：组合场效应和双极晶体管的门电路
公开(公告)号：US4829201A
公开(公告)日：1989-05-09
申请号：US127183
申请日：1987-12-01
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

5. 发明授权

US5600268A Gate circuit of combined field-effect and bipolar transistors 失效
标题翻译：组合场效应和双极晶体管的门电路
公开(公告)号：US5600268A
公开(公告)日：1997-02-04
申请号：US315594
申请日：1994-09-30
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H01L27/06 , H03K19/01 , H03K19/017 , H03K19/0944
CPC分类号： H03K19/09448 , H01L27/0623 , H03K19/01 , H03K19/01721
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.
摘要翻译：低功耗门电路结构包括互补场效应晶体管和双极型晶体管的组合，以及放电装置，用于当场效应晶体管和双极晶体管截止时从这些晶体管放电累积的电荷。

6. 发明授权

US5001366A Gate circuit of combined field-effect and bipolar transistors 失效
标题翻译：组合场效应和双极晶体管的门电路
公开(公告)号：US5001366A
公开(公告)日：1991-03-19
申请号：US127206
申请日：1987-12-01
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-space consumption gate circuit structure-comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

7. 发明授权

US5378941A Bipolar transistor MOS transistor hybrid semiconductor integrated circuit device 失效
标题翻译：双极晶体管MOS晶体管混合半导体集成电路器件
公开(公告)号：US5378941A
公开(公告)日：1995-01-03
申请号：US983467
申请日：1992-11-30
申请人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
发明人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/118 , H01L29/73 , H03K19/173 , H03K19/02 , H03K19/084
CPC分类号： H01L27/11896
摘要： A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input signals and supplying the signals to the internal circuits and a plurality of output circuits for receiving the output signals from the internal circuits and supplying signals to an external circuit. Each of the internal circuits is primarily constructed by bipolar transistors and MOS transistors, and at least one of each of the input circuits and each of the output circuits is primarily constructed by bipolar transistors.
摘要翻译：高速低功耗半导体集成电路器件具有多个内部电路，每个内部电路包括用于执行期望的电路操作的电路元件，用于接收外部输入信号并将信号提供给内部电路的多个输入电路和多个输出电路，用于接收来自内部电路的输出信号并向外部电路提供信号。每个内部电路主要由双极晶体管和MOS晶体管构成，并且每个输入电路和每个输出电路中的至少一个主要由双极晶体管构成。

8. 发明授权

US4527148A Analog-digital converter 失效
标题翻译：模数转换器
公开(公告)号：US4527148A
公开(公告)日：1985-07-02
申请号：US437303
申请日：1982-10-28
申请人： Shigeo Kuboki , Kazuo Kato , Nobuaki Miyakawa
发明人： Shigeo Kuboki , Kazuo Kato , Nobuaki Miyakawa
IPC分类号： H03M1/18 , G06F3/05 , H03M1/00 , H03K13/02 , H03K13/03
CPC分类号： H03M1/183 , H03M1/1215 , H03M1/46 , H03M1/76
摘要： An A/D converter used with an A/D conversion system in which each of input analog signals applied thereto is amplified at a gain selected depending or the level of said each signal and subjected to A/D conversion. The A/D converter is arranged to select a desired one of predetermined gain select modes concerned with the selection of gain of the amplifier. Further, the A/D converter produces a reference analog signal of a level corresponding to the selected gain select mode and compares the input analog signal with the reference analog signal, thereby determining whether or not the gain of the amplifier is to be changed.
摘要翻译： A / D转换器与A / D转换系统一起使用，其中施加到其中的每个输入模拟信号以所选择的增益或所述每个信号的电平进行放大，并进行A / D转换。 A / D转换器被配置为选择与放大器的增益选择有关的所需预定增益选择模式。此外，A / D转换器产生与所选择的增益选择模式相对应的电平的参考模拟信号，并将输入的模拟信号与参考模拟信号进行比较，从而确定放大器的增益是否被改变。

9. 发明授权

US4523180A Analog to digital converter 失效
标题翻译：模数转换器
公开(公告)号：US4523180A
公开(公告)日：1985-06-11
申请号：US277609
申请日：1981-06-26
申请人： Shigeo Kuboki , Kazuo Kato
发明人： Shigeo Kuboki , Kazuo Kato
IPC分类号： H03M1/38 , H03M1/00 , H03M1/20 , H03K13/02
CPC分类号： H03M1/38
摘要： In an analog to digital converter of the type wherein an analog input voltage is compared, at a comparator with a known reference voltage selected based on a digital data produced from a control circuit, an updated digital data is generated based on a result of the comparison, and the above operation is repeated to perform digital conversion sequentially from higher bit to lower bit, there are provided two capacitors of capacitances at a predetermined ratio which is so determined as to reduce the number of serial resistors in a voltage generator circuit adapted to generate the reference voltage based on the digital data produced from the control circuit, and a voltage developing at a junction between the two capacitors is coupled to the input of the comparator, so that a change in voltage of the voltage generator circuit is reduced at a predetermined ratio in accordance with electric charge distributed on the two capacitors and is applied to the input of the comparator.
摘要翻译：在比较模拟输入电压的模数转换器中，在基于从控制电路产生的数字数据选择的已知参考电压的比较器处，基于比较结果生成更新的数字数据，并且重复上述操作以从较高位到低位依次执行数字转换，以预定比例提供两个电容电容器，其被确定为减少适于产生的电压发生器电路中的串联电阻器的数量基于从控制电路产生的数字数据的参考电压和在两个电容器之间的结点处产生的电压被耦合到比较器的输入端，使得电压发生器电路的电压变化在预定的根据分配在两个电容器上的电荷的比例，并将其应用于比较器的输入。

10. 发明授权

US4604899A Semiconductor-type pressure transducer 失效
标题翻译：半导体式压力传感器
公开(公告)号：US4604899A
公开(公告)日：1986-08-12
申请号：US597753
申请日：1984-04-06
申请人： Kazuji Yamada , Hideo Sato , Kanji Kawakami , Kazuo Kato , Takao Sasayama
发明人： Kazuji Yamada , Hideo Sato , Kanji Kawakami , Kazuo Kato , Takao Sasayama
IPC分类号： G01R27/02 , G01B7/16 , G01D3/028 , G01L1/22 , G01L9/00 , G01L9/04 , G01L9/06 , G01L19/04
CPC分类号： G01L1/2281 , G01L9/065
摘要： A semiconductor-type pressure transducer is disclosed in which the pressure change is detected as a resistance change by use of a bridge circuit including at least a gauge resistor changing with an external force. Each gauge resistor is made of a PN junction of a semiconductor. The pressure transducer further comprises an amplification factor compensator for cancelling the effect of the temperature change of the gauge resistors making up the bridge circuit on the amplification factor of the amplification circuit for amplifying the output of the bridge circuit.
摘要翻译：公开了一种半导体型压力传感器，其中通过使用至少包括用外力改变的量规电阻器的桥式电路将压力变化检测为电阻变化。每个规格电阻由半导体的PN结制成。压力传感器还包括放大系数补偿器，用于抵消构成桥式电路的量规电阻器的温度变化对放大电路的放大系数的影响，用于放大桥式电路的输出。

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